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HALT
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
INC Mn
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
S1C6200/6200A CORE CPU MANUAL
Halt
HALT
Stops CPU
1 1 1 1 1 1 1 1 1 0 0 0
MSB
VI
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Stops the CPU. When an interrupt occurs, PCP and PCS are pushed onto the
stack as the return address and the interrupt service routine is executed.
Instruction
HALT
Interrupt
Increment memory by 1
INC Mn
M(n
to n
)
M(n
to n
3
0
3
1 1 1 1 0 1 1 0 n
MSB
IV
7
C –
Set if a carry is generated; otherwise, reset.
Z –
Set if the result is zero; otherwise, reset.
D –
Not affected
I –
Not affected
The contents of the data memory location addressed by Mn is incremented by 1.
INC M1
Memory (01H)
0100
Memory (03H)
1111
Memory (0DH)
0111
C flag
0
Z flag
1
FF8H
LSB
State
PCP
RUN
0001
HALT
0001
RUN
0001
Interrupt vector address
) + 1
0
n
n
n
F60H to F6FH
3
2
1
0
LSB
INC M3
0101
1111
0111
0
0
EPSON
3 INSTRUCTION SET
PCS
I flag
0011 0011
1
0011 0100
1
0
INC M0DH
0101
0101
0000
0000
0111
1000
1
0
1
0
41
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