Epson 6200A Core Cpu Manual page 24

3 INSTRUCTION SET
Mne-
Classification Operand
monic
B
Index
CP XH, i
operation XL, i
instructions
YH, i
YL, i
Data
LD r, i
transfer r, q
instructions
A, Mn
B, Mn
Mn, A
Mn, B
LDPX MX, i
r, q
LDPY MY, i
r, q
LBPX MX, e
Flag SET F, i
operation
RST F, i
instructions SCF
RCF
SZF
RZF
SDF
RDF
EI
DI
Stack INC SP
operation
DEC SP
instructions PUSH r
XP
XH
XL
YP
YH
YL
F
r
POP
XP
XH
XL
YP
18
Operation Code
A 9 8 7 6 5 4 3 2
1 0 1 0 0 1 0 0 i3 i2
1 0 1 0 0 1 0 1 i3 i2
1 0 1 0 0 1 1 0 i3 i2
1 0 1 0 0 1 1 1 i3 i2
1 1 1 0 0 0 r1 r0 i3 i2
1 1 1 0 1 1 0 0 r1 r0
1 1 1 1 1 0 1 0 n3 n2
1 1 1 1 1 0 1 1 n3 n2
1 1 1 1 1 0 0 0 n3 n2
1 1 1 1 1 0 0 1 n3 n2
1 1 1 0 0 1 1 0 i3 i2
1 1 1 0 1 1 1 0 r1 r0
1 1 1 0 0 1 1 1 i3 i2
1 1 1 0 1 1 1 1 r1 r0
1 0 0 1 e7 e6 e5 e4 e3 e2
1 1 1 1 0 1 0 0 i3 i2
1 1 1 1 0 1 0 1 i3 i2
1 1 1 1 0 1 0 0 0 0
1 1 1 1 0 1 0 1 1 1
1 1 1 1 0 1 0 0 0 0
1 1 1 1 0 1 0 1 1 1
1 1 1 1 0 1 0 0 0 1
1 1 1 1 0 1 0 1 1 0
1 1 1 1 0 1 0 0 1 0
1 1 1 1 0 1 0 1 0 1
1 1 1 1 1 1 0 1 1 0
1 1 1 1 1 1 0 0 1 0
1 1 1 1 1 1 0 0 0 0
1 1 1 1 1 1 0 0 0 1
1 1 1 1 1 1 0 0 0 1
1 1 1 1 1 1 0 0 0 1
1 1 1 1 1 1 0 0 0 1
1 1 1 1 1 1 0 0 1 0
1 1 1 1 1 1 0 0 1 0
1 1 1 1 1 1 0 0 1 0
1 1 1 1 1 1 0 1 0 0
1 1 1 1 1 1 0 1 0 1
1 1 1 1 1 1 0 1 0 1
1 1 1 1 1 1 0 1 0 1
1 1 1 1 1 1 0 1 0 1
Flag
Clock
1 0 I D Z C
XH-i3~i0
i1 i0 7
i1 i0 7 XL-i3~i0
YH-i3~i0
i1 i0 7
i1 i0 7 YL-i3~i0
r i3~i0
i1 i0 5
q1 q0 5 r q
A M(n3~n0)
n1 n0 5
n1 n0 5 B M(n3~n0)
M(n3~n0)
n1 n0 5
n1 n0 5 M(n3~n0)
M(X)
i1 i0 5
q1 q0 5 r q, X
M(Y)
i1 i0 5
q1 q0 5 r q, Y
M(X)
e1 e0 5
i1 i0 7 F FVi3~i0
F F i3~i0
i1 i0 7
0 1 7 C 1
C 0
1 0 7
1 0 7 Z 1
Z 0
0 1 7
0 0 7 D 1 (Decimal Adjuster ON)
D 0 (Decimal Adjuster OFF)
1 1 7
0 0 7 I 1 (Enables Interrupt)
I 0 (Disables Interrupt)
1 1 7
1 1 5 SP SP+1
SP SP-1
1 1 5
r1 r0 5 SP SP-1, M(SP)
SP SP-1, M(SP)
0 0 5
0 1 5 SP SP-1, M(SP)
SP SP-1, M(SP)
1 0 5
1 1 SP SP-1, M(SP)
5
SP SP-1, M(SP)
0 0 5
0 1 SP SP-1, M(SP)
5
SP SP-1, M(SP)
1 0 5
r M(SP), SP
r1 r0 5
XP M(SP), SP
0 0 5
XH M(SP), SP
0 1 5
XL M(SP), SP
1 0 5
YP M(SP), SP
1 1 5
EPSON
Operation
A
B
i3~i0, X X+1
X+1
i3~i0, Y Y+1
Y+1
e3~e0, M(X+1) e7~e4, X X+2
r
XP
XH
XL
YP
YH
YL
F
SP+1
SP+1
SP+1
SP+1
SP+1
S1C6200/6200A CORE CPU MANUAL