Epson 6200A Core Cpu Manual page 73

Core cpu cmos 4-bit single chip microcomputer
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POP YP
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
PSET p
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
S1C6200/6200A CORE CPU MANUAL
Pop stack data into YP
POP YP
YP
M(SP), SP
SP + 1
1 1 1 1 1 1 0 1
MSB
VI
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Loads the contents of the data memory location addressed by the stack pointer
into YP, the 4-bit page part of IY. SP is incremented by 1.
SP
C0
Memory (C0H)
0000
YP register
0001
Page set
PSET p
NBP
p
, NPP
p
to p
4
3
1 1 1 0 0 1 0 p
MSB
III
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Loads the most-significant bit of the 5-bit immediate data p to the new bank
pointer (NBP) and the four low-order bits to the new page pointer (NPP).
PSET 1FH
PCB
0
NBP
0
PCP
1000
NPP
0001
PCS
0010 0011
0 1 1 1
FD7H
LSB
M(SP) =
POP YP
C1
0000
0000
0
p
p
p
p
E40H to E5FH
4
3
2
1
0
LSB
JP 00H
0
1
1000
1111
0010 0100
0000 0000
EPSON
3 INSTRUCTION SET
3
2
1
0
2
2
2
2
2
0
1
2
2
2
2
3
1
1
1111
1111
= YP
67

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