Epson 6200A Core Cpu Manual page 89

ABBREVIATIONS
Source Format:
A ............. A register (4 bits)
B ............. B register (4 bits)
Operation:
M(SP) ..... Contents of the data memory location whose address is specified by stack pointer SP (4 bits)
OP-Code:
M(X) ....... Contents of the data memory location whose address is specified by IX (4 bits)
M(Y) ....... Contents of the data memory location whose address is specified by IY (4 bits)
Type:
M(n - ) .... Contents of the data memory location within the register area 00H to 0FH (4 bits)
3 0
Clock Cycles:
MX .......... Data memory location whose address is specified by IX
MY .......... Data memory location whose address is specified by IY
Flag:
NBP ........ New Bank Pointer (1 bit)
NPP ........ New Page Pointer (4 bits)
PCB ........ Program Counter-Bank (1 bit)
Description:
PCP ........ Program Counter-Page (4 bits)
PCS ........ Program Counter-Step (8 bits)
PCSH ..... Four high-order bits of PCS
PCSL ...... Four low-order bits of PCS Example:
RP .......... Register Pointer (4 bits)
SP .......... Stack Pointer (8 bits)
SPH ........ Four high-order bits of SP
SPL ........ Four low-order bits of SP
X ............. Eight low-order bits of IX, that is, XHL
XH .......... Four high-order bits of X
XL ........... Four low-order bits of X
XP .......... Four high-order bits of IX (page part)
Y ............. Eight low-order bits of IY, that is, YHL
Source Format:
YH .......... Four high-order bits of Y
YL ........... Four low-order bits of Y
Operation:
YP .......... Four high-order bits of IY (page part)
OP-Code:
+ ............. Addition
– ............. Subtraction
Type:
Logical AND
Clock Cycles:
............. Logical OR
Flag:
............. Exclusive-OR
............. Reset flag
............. Set flag
............. Set/reset flag
Description:
............. Decimal addition/subtraction
Example:
S1C6200/6200A CORE CPU MANUAL
MSB
C –
Z –
D –
I –
MSB
C –
Z –
D –
I –
LSB
LSB
EPSON
3 INSTRUCTION SET
83