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LD r,i
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
LD r,q
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
S1C6200/6200A CORE CPU MANUAL
Load immediate data i into r-register
LD r,i
r
i
to i
3
0
1 1 1 0 0 0 r
MSB
II
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Loads immediate data i into the r-register.
LD A,6
A register
0101
Memory (MY)
1001
Load q-register into r-register
LD r,q
r
q
1 1 1 0 1 1 0 0 r
MSB
IV
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
The contents of the q-register are loaded into the r-register.
LD A,B
A register
0010
B register
0000
Memory (MY)
0110
r
i
i
i
i
1
0
3
2
1
0
LSB
LD MY,0
0110
1001
r
q
q
1
0
1
0
LSB
LD B,MY
0000
0000
0110
EPSON
3 INSTRUCTION SET
E00H to E3FH
0110
0000
EC0H to ECFH
0000
0110
0110
51
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