Epson 6200A Core Cpu Manual page 56

Core cpu cmos 4-bit single chip microcomputer
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3 INSTRUCTION SET
LDPY MY,i
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
LDPY r,q
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
50
Load immediate data i into MY, increment Y by 1
LDPY MY,i
M(Y)
i
to i
, Y
Y + 1
3
0
1 1 1 0 0 1 1 1
MSB
IV
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Loads immediate data i into the data memory location addressed by IY. Y is
incremented by 1. Incrementing Y does not affect the flags.
LDPY MY,7
Y register
0010 1101
Memory (2DH)
1010
Memory (2EH)
0010
Load q-register into r-register, increment Y by 1
LDPY r,q
r
q, Y
Y + 1
1 1 1 0 1 1 1 1
MSB
IV
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Loads the contents of the q-register into the r-register. Y is incremented by 1.
Incrementing Y does not affect the flags.
LDPY A,B
Y register
0100 1000
A register
1010
B register
1000
Memory (MX)
0010
i
i
i
i
E70H to E7FH
3
2
1
0
LSB
LDPY MY,0
0010 1110
0010 1111
0111
0111
0010
0000
r
r
q
q
EF0H to EFFH
1
0
1
0
LSB
LDPY MX,B
0100 1001
0100 1010
1000
1000
1000
1000
0010
1000
EPSON
S1C6200/6200A CORE CPU MANUAL

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