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JP NZ,s
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
JP s
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
S1C6200/6200A CORE CPU MANUAL
Jump if not zero
JP NZ,s
PCB
NBP, PCP
NPP, PCS
0 1 1 1 s
s
s
7
6
MSB
I
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Jumps to the destination address specified by the 8-bit operand when the zero flag
is not set.
JP NZ,10H
PCB
1
NBP
1
PCP
0000
NPP
0000
PCS
0000 0111
Z flag
0
Jump
JP s
PCB
NBP, PCP
NPP, PCS
0 0 0 0 s
s
s
7
6
MSB
I
5
C –
Not affected
Z –
Not affected
D –
Not affected
I –
Not affected
Unconditional jump to the destination address specified by the 8-bit operand.
PSET 0AH
PCB
0
NBP
0
PCP
0000
NPP
0001
PCS
0100 0010
s
to s
if Z = 0
7
0
s
s
s
s
s
5
4
3
2
1
0
LSB
1
1
0000
0000
0001 0000
0
s
to s
7
0
s
s
s
s
s
5
4
3
2
1
0
LSB
JP 10H
0
0
0000
1010
0100 0011
0001 0000
EPSON
3 INSTRUCTION SET
700H to 7FFH
000H to 0FFH
0
0
1010
1010
45
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