By Operation Code - Epson 6200A Core Cpu Manual

Core cpu cmos 4-bit single chip microcomputer
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3.1.3 By operation code

Operation
Mne-
Operand
Code (HEX)
monic
B
000 to 0FF
JP
s
0
100 to 1FF
RETD
e
0
200 to 2FF
JP
C, s
0
300 to 3FF
JP
NC, s
0
400 to 4FF
CALL
s
0
500 to 5FF
CALZ
s
0
600 to 6FF
JP
Z, s
0
700 to 7FF
JP
NZ, s
0
800 to 8FF
LD
Y, e
1
900 to 9FF
LBPX
MX, e
1
A00 to A0F
ADC
XH, i
1
A10 to A1F
ADC
XL, i
1
A20 to A2F
ADC
YH, i
1
A30 to A3F
ADC
YL, i
1
A40 to A4F
CP
XH, i
1
A50 to A5F
CP
XL, i
1
A60 to A6F
CP
YH, i
1
A70 to A7F
CP
YL, i
1
A80 to A8F
ADD
r, q
1
A90 to A9F
ADC
r, q
1
AA0 to AAF
SUB
r, q
1
AB0 to ABF
SBC
r, q
1
AC0 to ACF
AND
r, q
1
AD0 to ADF
OR
r, q
1
AE0 to AEF
XOR
r, q
1
AF0 to AFF
RLC
r
1
B00 to BFF
LD
X, e
1
C00 to C3F
ADD
r, i
1
C40 to C7F
r, i
1
ADC
C80 to CBF
AND
r, i
1
CC0 to CFF
r, i
1
OR
D00 to D3F
XOR
r, i
1
D0F to D3F
r
1
NOT
D40 to D7F
SBC
r, i
1
D80 to DBF
r, i
1
FAN
DC0 to DFF
CP
r, i
1
E00 to E3F
LD
r, i
1
S1C6200/6200A CORE CPU MANUAL
Operation Code
A
9
8
7
6
5
4
3
2
1
0
0
0
s7
s6
s5
s4
s3
s2
s1
0
0
1
e7
e6
e5
e4
e3
e2
e1
0
1
0
s7
s6
s5
s4
s3
s2
s1
0
1
1
s7
s6
s5
s4
s3
s2
s1
1
0
0
s7
s6
s5
s4
s3
s2
s1
1
0
1
s7
s6
s5
s4
s3
s2
s1
1
1
0
s7
s6
s5
s4
s3
s2
s1
1
1
1
s7
s6
s5
s4
s3
s2
s1
0
0
0
e7
e6
e5
e4
e3
e2
e1
0
0
1
e7
e6
e5
e4
e3
e2
e1
0
1
0
0
0
0
0
i3
i2
i1
0
1
0
0
0
0
1
i3
i2
i1
0
1
0
0
0
1
0
i3
i2
i1
0
1
0
0
0
1
1
i3
i2
i1
0
1
0
0
1
0
0
i3
i2
i1
0
1
0
0
1
0
1
i3
i2
i1
0
1
0
0
1
1
0
i3
i2
i1
0
1
0
0
1
1
1
i3
i2
i1
0
1
0
1
0
0
0
r1
r0
q1
0
1
0
1
0
0
1
r1
r0
q1
0
1
0
1
0
1
0
r1
r0
q1
0
1
0
1
0
1
1
r1
r0
q1
0
1
0
1
1
0
0
r1
r0
q1
0
1
0
1
1
0
1
r1
r0
q1
0
1
0
1
1
1
0
r1
r0
q1
0
1
0
1
1
1
1
r1
r0
r1
0
1
1
e7
e6
e5
e4
e3
e2
e1
1
0
0
0
0
r1
r0
i3
i2
i1
1
0
0
0
1
r1
r0
i3
i2
i1
1
0
0
1
0
r1
r0
i3
i2
i1
1
0
0
1
1
r1
r0
i3
i2
i1
1
0
1
0
0
r1
r0
i3
i2
i1
1
0
1
0
0
r1
r0
1
1
1
1
0
1
0
1
r1
r0
i3
i2
i1
1
0
1
1
0
r1
r0
i3
i2
i1
1
0
1
1
1
r1
r0
i3
i2
i1
1
1
0
0
0
r1
r0
i3
i2
i1
Flag
Clock
0
I D Z C
s0
5
PCB
NBP, PCP
e0
12
PCSL
M(SP), PCSH
SP
SP+3, M(X)
s0
5
PCB
NBP, PCP
s0
5
PCB
NBP, PCP
s0
7
M(SP-1)
SP
SP-3, PCP
s0
7
M(SP-1)
SP
SP-3, PCP
s0
5
PCB
NBP, PCP
s0
5
PCB
NBP, PCP
e0
5
YH
e7~e4, YL
e0
5
M(X)
e3~e0, M(X+1)
i0
7
XH
XH+i3~i0+C
i0
7
XL
XL+i3~i0+C
i0
7
YH
YH+i3~i0+C
i0
7
YL
YL+i3~i0+C
i0
7
XH-i3~i0
i0
7
XL-i3~i0
i0
7
YH-i3~i0
i0
7
YL-i3~i0
q0
7
r
r+q
q0
7
r
r+q+C
q0
7
r
r-q
q0
7
r
r-q-C
q0
7
r
r q
q0
7
r
rVq
q0
r
r q
7
r0
7
d3
d2, d2
e0
XH
e7~e4, XL
5
i0
7
r
r+i3~i0
i0
r
r+i3~i0+C
7
i0
7
r
r i3~i0
i0
r
rVi3~i0
7
i0
7
r
r i3~i0
1
r
r
7
i0
7
r
r-i3~i0-C
i0
r i3~i0
7
i0
7
r-i3~i0
r
i3~i0
i0
5
EPSON
3 INSTRUCTION SET
Operation
NPP, PCS
s7~s0
M(SP+1), PCP
e3~e0, M(X+1)
e7~e4, X
NPP, PCS
s7~s0 if C=1
NPP, PCS
s7~s0 if C=0
PCP, M(SP-2)
PCSH, M(SP-3)
NPP, PCS
s7~s0
PCP, M(SP-2)
PCSH, M(SP-3)
0, PCS
s7~s0
NPP, PCS
s7~s0 if Z=1
NPP, PCS
s7~s0 if Z=0
e3~e0
e7~e4, X
X+2
d1, d1
d0, d0
C, C
d3
e3~e0
M(SP+2)
X+2
PCSL+1
PCSL+1
23

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