Epson 6200A Core Cpu Manual page 59

LD r,XH
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
LD r,XL
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
S1C6200/6200A CORE CPU MANUAL
Load XH into r-register
LD r,XH
r XH
1 1 1 0 1 0 1 0 0 1 r
MSB
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Loads the four high-order bits of register X into the r-register.
LD B,XH
XH register 1010
B register 0010
Memory (MX) 0000
Load XL into r-register
LD r,XL
r XL
1 1 1 0 1 0 1 0 1 0 r
MSB
V
5
C – Not affected
Z – Not affected
D – Not affected
I – Not affected
Loads the four low-order bits of register X into the r-register.
LD MY,XL
XL register 0000
A register 1101
Memory (MY) 0001
r EA4H to EA7H
1 0
LSB
LD MX,XH
1010 1010
1010 1010
0000 1010
r EA8H to EABH
1 0
LSB
LD A,XL
0000 0000
1101 0000
0000 0000
EPSON
3 INSTRUCTION SET
53