And R,I; Logical And Immediate Data I With R-Register; And R,Q; Logical And Q-Register With R-Register - Epson 6200A Core Cpu Manual

AND r,i

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:

AND r,q

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
S1C6200/6200A CORE CPU MANUAL

Logical AND immediate data i with r-register

AND r,i
r r i to i
3 0
1 1 0 0 1 0 r
MSB
II
7
C – Not affected
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Performs a logical AND operation between immediate data i and the contents of
the r-register. The result is stored in the r-register.
AND A,5
A register 0110
Memory (MX) 1000
C flag 1
Z flag 0

Logical AND q-register with r-register

AND r,q
r r q
1 0 1 0 1 1 0 0 r
MSB
IV
7
C – Not affected
Z – Set if the result is zero; otherwise, reset.
D – Not affected
I – Not affected
Performs a logical AND operation between the contents of the q-register and the
contents of the r-register. The result is stored in the r-register.
AND MX,A
A register 0100
B register 1011
Memory (MX) 1010
Memory (MY) 0010
C flag 0
Z flag 0
r i i i i0
1 0 3 2 1
LSB
AND MX,3
0100
1000
1
0
r q q
1 0 1 0
LSB
AND B,MY
0100
1011
0000
0010
0
1
EPSON
3 INSTRUCTION SET
C80H to CBFH
0100
0000
1
1
AC0H to ACFH
0100
0010
0000
0010
0
0
33