Epson 6200A Core Cpu Manual page 20

2 MEMORY AND OPERATIONS
S1C6200/6200A
System clock
CPU clock
Status
Instruction
5-clock Instrruction
Status:
S1C6200
Clock
Status
Instruction
S1C6200A
Clock
Status
Instruction
Status:
14
SLEEP
Fetch Execute Note:
Fig. 2.5.3.3 Interrupt timing in SLEEP mode
PSET CALL
Interrupt
Interrupt processing:
PSET CALL
Interrupt
Interrupt processing:
Fetch Execute Note:
Fig. 2.5.3.4 Interrupt timing with PSET
INT1 (*1)
Interrupt
Interrupt processing: 14 to 15 clock cycles
(*1) INT1 and INT2 are dummy instructions
Branches to the top of the interrupt service routine
(*2)
INT1 (*1) INT2 (*1)
PSET + CALL ... 13 to 25 clock cycles
PSET + JP ... 13 to 23 clock cycles
INT1 (*1) INT2 (*1)
PSET + CALL ... 12.5 to 24.5 clock cycles
PSET + JP ... 12.5 to 22.5 clock cycles
(*1) INT1 and INT2 are dummy instructions
Branches to the top of the interrupt service routine
(*2)
EPSON
INT2 (*1) JP (*2)
JP (*2)
JP (*2)
S1C6200/6200A CORE CPU MANUAL