Interrupts And Exceptions; Priority Of Exceptions - Epson S1C33 Series Core Manual

6 FUNCTIONS

6.3 Interrupts and Exceptions

When an external interrupt or exception occurs during program execution, the processor enters an exception
handling state. The exception handling state is a process by which the processor branches to the corresponding
user's service routine for the interrupt or exception that occurred. The processor returns after branching and starts
executing the program from where it left off.

6.3.1 Priority of Exceptions

The following exception handlings are supported by the C33 PE Core:
(1) Reset, internal exceptions of the processor, and external interrupts for which the processor branches to the
relevant exception handler routine by referencing the vector table
(2) Debug exceptions such as breaks that are provided to support debugging by the user
The priority of these exceptions is listed in the table below.
Reset
Address misaligned exception
Undefined instruction exception
ext exception
Debug exception
NMI
Software exception
Maskable external interrupt
When two or more exceptions occur simultaneously, they are processed in order of priority beginning with the one
that has the highest priority.
When an exception occurs, the processor disables interrupts that would occur thereafter and performs exception
handling. To support multiple interrupts (or another interrupt from within an interrupt), set the IE flag in the PSR
to 1 in the exception handler routine to enable interrupts during exception handling. Basically, even when multiple
interrupts are enabled, interrupts and exceptions whose priorities are below the one set by the IL[3:0] bits in the
PSR are not accepted.
The debug exception has its vector located at the specific addresses, and the vector table is not referenced for this
exception. Nor is the stack used for the PC, and the PC is saved in a specific area along with R0.
The table below shows the addresses that are referenced when a debug exception occurs.
Table 6.3.1.2 Debug Exception Vector Address and PC/R0 Save Area
During debug exception handling, neither other exceptions nor multiple debug exceptions are accepted. They are
kept pending until the debug exception handling currently underway finishes.
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Table 6.3.1.1 Vector Address and Priority of Exceptions
Exception
TTBR + 0x40 to TTBR + 0x3FC
Address
0x00060000
0x00060008
0x0006000C
Vector address (Hex)
TTBR + 0x00
TTBR + 0x18
TTBR + 0x0C
TTBR + 0x08
0x00060000
TTBR + 0x1C
TTBR + 0x30 to TTBR + 0x3C
Content
Debug exception handler vector
PC save area
R0 save area
EPSON
Priority
High
Low
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