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3 INSTRUCTION SET
ACPX MX,r
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
ACPY MY,r
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
28
Add with carry r-register to M(X), increment X by 1
ACPX MX,r
M(X)
M(X) + r + C, X
1 1 1 1 0 0 1 0 1 0 r
MSB
V
7
C –
Set if a carry is generated; otherwise, reset.
Z –
Set if the result is zero; otherwise, reset.
D –
Not affected
I –
Not affected
Adds the carry bit and the contents of the r-register to the data memory location
addressed by IX. X is incremented by one. Incrementing X does not affect the
flags.
ACPX MX,A
X register
1010 0000
Y register
0100 0110
Memory (A0H)
0110
Memory (A1H)
0011
Memory (46H)
0100
A register
1000
C flag
1
Z flag
0
Add with carry r-register to M(Y), increment Y by 1
ACPY MY,r
M(Y)
M(Y) + r + C, Y
1 1 1 1 0 0 1 0 1 1 r
MSB
V
7
C –
Set if a carry is generated; otherwise, reset.
Z –
Set if the result is zero; otherwise, reset.
D –
Not affected
I –
Not affected
Adds the carry bit and the contents of the r-register to the data memory location
addressed by IY. Y is incremented by one. Incrementing Y does not affect the
flags.
ACPY MY,A
X register
0010 0001
Y register
0000 1110
Memory (0EH)
1000
Memory (0FH)
0100
Memory (21H)
0110
A register
0010
C flag
1
Z flag
0
X + 1
r
F28H to F2BH
1
0
LSB
ACPX MX,MY
1010 0001
1010 0010
0100 0110
0100 0110
1111
1111
0011
0111
0100
0100
1000
1000
0
0
Y + 1
r
F2CH to F2FH
1
0
LSB
ACPY MY,MX
0010 0001
0010 0001
0000 1111
0001 0000
1011
1011
0100
1010
0110
0110
0010
0010
0
0
EPSON
0
0
0
0
S1C6200/6200A CORE CPU MANUAL
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