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Electrical Specifications
Table 2-1.
Core Frequency to FSB Multiplier Configuration
Core Frequency to FSB
Multiplier
Notes:
1.
Individual processors operate only at or below the frequency marked on the package.
2.
Listed frequencies are not necessarily committed production frequencies.
3.
For valid processor core frequencies, refer to the Dual-Core Intel® Xeon® Processor 7200 Series and
Quad-Core Intel® Xeon® Processor 7300 Series Specification Update.
4.
The lowest bus ratio supported is 1/6.
2.3.1
Front Side Bus Frequency Select Signals (BSEL[2:0])
Upon power up, the FSB frequency is set to the maximum supported by the individual
processor. BSEL[2:0] are CMOS outputs that are used to select the FSB frequency.
Please refer to
combinations of the signals and the frequency associated with each combination. The
frequency is determined by the processor(s), chipset, and clock synthesizer. All FSB
agents must operate at the same core and FSB frequency. See the appropriate
platform design guidelines for further details.
Table 2-2.
BSEL[2:0] Frequency Table
BSEL2
2.3.2
PLL Power Supply
An on-die PLL filter solution is implemented on the processor. The
to provide power to the on chip PLL of the processor. Please refer to
specifications. Refer to the appropriate platform design guidelines for decoupling and
routing guidelines.
2.4
Voltage Identification (VID)
The Voltage Identification (VID) specification for the processor is defined by the
Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0
Design Guidelines. The voltage set by the VID signals is the reference VR output
voltage to be delivered to the processor Vcc pins. VID signals are asynchronous CMOS
Document Number: 318080-002
Core Frequency with
266 MHz FSB Clock
1/6
1/7
1/8
1/9
1/10
1/11
Table 2-11
for DC specifications.
BSEL1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
1.60 GHz
1.86 GHz
2.13 GHz
2.40 GHz
2.66 GHz
2.93 GHz
Table 2-2
BSEL0
0
1
0
1
0
1
0
1
Notes
1, 2, 3, 4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
defines the possible
Bus Clock Frequency
266 MHz
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
input is used
V
CCPLL
Table 2-9
for DC
17
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