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Electrical Specifications
9.
Minimum VCC and maximum ICC are specified at the maximum processor case temperature (TCASE)
shown in
10. This specification refers to the total reduction of the load line due to VID transitions below the specified
VID.
11. Individual processor VID values may be calibrated during manufacturing such that two devices at the same
frequency may have different VID settings.
12. This specification applies to the VCCPLL pin.
13. Baseboard bandwidth is limited to 20 MHz.
14. I
CC_TDC
should be used for the voltage regulator temperature assessment. The voltage regulator is responsible for
monitoring its temperature and asserting the necessary signal to inform the processor of a thermal
excursion. Please see the applicable design guidelines for further details. The processor is capable of
drawing I
over various time durations. This parameter is based on design characterization and is not tested.
15. This is the maximum total current drawn from the V
specification does not include the current coming from on-board termination (R
Refer to the appropriate platform design guide and the Voltage Regulator Design Guidelines to determine
the total I
16. I
_
CC
VTT
17. I
CC_RESET
RESET# de-assertion time specification and
Figure 2-1.
Quad-Core Intel® Xeon® L7345 Processor Load Current versus Time
Notes:
1.
Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than
I
CC_TDC
2.
Not 100% tested. Specified by design characterization.
Document Number: 318080-002
Figure
6-2.
is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and
indefinitely. Refer to
CC_TDC
drawn by the system. This parameter is based on design characterization and is not tested.
TT
is specified at 1.2 V.
_
OUT
is specified while PWRGOOD and RESET# are asserted. Refer to
65
60
55
50
45
40
0.01
0.1
.
Figure 2-9
for further details on the average processor current draw
plane by only one processor with R
TT
Table 2-23
for the RESET# Pulse Width specification.
1
10
Tim e Duration (s)
enabled. This
TT
), through the signal line.
TT
Table 2-22
for the PWRGOOD to
100
1000
27
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