Front Side Bus Agtl+ Decoupling; Front Side Bus Clock (Bclk[1:0]) And Processor Clocking - Intel E5310 - Xeon 1.6 GHz 8M L2 Cache 1066MHz FSB LGA771 Active Quad-Core Processor Datasheet

Electrical Specifications
2.3.3

Front Side Bus AGTL+ Decoupling

The processor integrates signal termination on the die, as well as a portion of the
required high frequency decoupling capacitance on the processor package. However,
additional high frequency capacitance must be added to the baseboard to properly
decouple the return currents from the FSB. Bulk decoupling must also be provided by
the baseboard for proper AGTL+ bus operation. Decoupling guidelines are described in
the appropriate platform design guidelines.
2.4 Front Side Bus Clock (BCLK[1:0]) and Processor
Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous processor generations, the processor core frequency is a
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier is set during
manufacturing. The default setting is for the maximum speed of the processor. It is
possible to override this setting using software (see the Intel® 64 and IA-32
Architectures Software Developer's Manual). This permits operation at lower
frequencies than the processor's tested frequency.
The processor core frequency is configured during reset by using values stored
internally during manufacturing. The stored value sets the highest bus fraction at which
the particular processor can operate. If lower speeds are desired, the appropriate ratio
can be configured via the CLOCK_FLEX_MAX Model Specific Register (MSR). For details
of operation at core frequencies lower than the maximum rated processor speed, refer
to the Intel® 64 and IA-32 Architectures Software Developer's Manual.
Clock multiplying within the processor is provided by the internal phase locked loop
(PLL), which requires a constant frequency BCLK[1:0] input, with exceptions for spread
spectrum clocking. Processor DC and AC specifications for the BCLK[1:0] inputs are
provided in
integrity requirements as outlined in
clocks. Table 2-1
corresponding core frequencies.
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
Table 2-19. These specifications must be met while also meeting signal
contains processor core frequency to FSB multipliers and their
Table 2-19. The processor utilizes differential
17