Clock Specifications; Front Side Bus Clock (Bclk[1:0]) And Processor Clocking; Core Frequency To Fsb Multiplier Configuration - Intel E8200 - Cpu Core 2 Duo 2.66Ghz Fsb1333Mhz 6M Lga775 Tray Datasheet

Electrical Specifications
2.8

Clock Specifications

2.8.1

Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the processor core frequency is a
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its
default ratio during manufacturing. The processor supports Half Ratios between 7.5
and 13.5, refer to
The processor uses a differential clocking implementation. For more information on the
processor clocking, contact your Intel field representative.
Table 16.

Core Frequency to FSB Multiplier Configuration

Multiplication of
System Core
Frequency to FSB
Frequency
NOTES:
1. Individual processors operate only at or below the rated frequency.
2. Listed frequencies are not necessarily committed production frequencies.
Datasheet
Table 16 for the processor supported ratios.
Core Frequency
(266 MHz BCLK/1066 MHz
1/6
1/7
1/7.5
1/8
1/8.5
1/9
1/9.5
1/10
1/10.5
1/11
1/11.5
1/12
1/12.5
1/13
1/13.5
1/14
1/15
Core Frequency
(333 MHz BCLK/
FSB)
1333 MHz FSB)
1.60 GHz
1.86 GHz
2 GHz
2.13 GHz
2.26 GHz
2.40 GHz
2.53 GHz
2.66 GHz
2.80 GHz
2.93 GHz
3.06 GHz
3.20 GHz
3.33 GHz
3.46 GHz
3.60GHz
3.73 GHz
4 GHz
Notes
2 GHz -
2.33 GHz -
2.50 GHz -
2.66 GHz -
2.83 GHz -
3 GHz -
3.16 GHz -
3.33 GHz -
3.50 GHz -
3.66 GHz -
3.83 GHz -
4 GHz -
4.16 GHz -
4.33 GHz -
4.50 GHz -
4.66 GHz -
5 GHz -
1, 2
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