Part 3.11: Pcie Slot - Alinx UltraScale+ AXU4EV-P User Manual

Part 3.11: PCIe Slot

There is a PCIe x2 interface on the AXU4EV-P carrier board, and two pairs
of transceivers are connected to the PCIEx2, which can realize PCIE 3.0
(compatible 2.0 ) data communication.
The transceiver signal of the PCIe interface is directly connected to the
GTH transceiver of ZYNQ BANK224, and the single-channel communication
rate can be as high as 8G bit bandwidth.
The PCIe interface schematic is shown in Figure 3-11 below, where the TX
signal is connected in AC coupling mode.
ZYNQ
Ultrascale+
PCIe x2 Interface ZYNQ Pin Assignment
Signal Name
PCIE_RX0_N
PCIE_RX0_P
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ZYNQ Ultrascale + FPGA Board AXU4EV-P User Manual
U1
BANK224
GTH
收发器
BANK43
Figure 3-11: PCIe Interface Schematic
ZYNQ Pin Name
224_RX2_N
224_RX2_P
PCIE_TX1_P/N
PCIE_TX0_P/N
PCIE_RX1_P/N
PCIE_RX0_P/N
PCIE_PERST
ZYNQ Pin
Number
T1 PCIE Channel 0 Data Receive Negative
T2 PCIE Channel 0 Data Receive Positive
PCIE x 2金手指
Description
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