Part 3.3: Sfp Interface - Alinx AX7A035 User Manual

ETH_RXD1
ETH_RXD2
ETH_RXD3
ETH_RXCTL
ETH_MDC
ETH_MDIO
ETH_RESET

Part 3.3: SFP Interface

The AX7A035 FPGA development board has two optical interfaces. Users
can purchase SFP optical modules (1.25G, 2.5G optical modules on the market)
and insert them into these two optical interfaces for optical data communication.
The two fiber interfaces are connected to the two RX/TX of the GNK
transceiver of the FPGA. The TX signal and the RX signal are connected to the
FPGA and the optical module through the DC blocking capacitor in differential
signal mode. The TX and RX data rates are up to each 6.6Gb/s per channel.
The reference clock for the GTX transceiver is provided by the 125Mhz
differential clock of AC7A035 FPGA core board.
Figure 3-3-1 detailed the schematic diagram of FPGA and fiber design
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ARTIX-7 FPGA Development Board AX7A035 User Manual
Figure 3-3-1: SFP Interface Schematic
U18
U17
P17
Receive data valid signal
R19
MDIO Management Clock
N13
MDIO Management Data
P14
PHY Chip Reset Signal
R14
Receive Data Bit1
Receive Data Bit2
Receive Data Bit3
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