Alinx AX7A035 User Manual page 28

Board to Board Connectors CON3
The 80-pin connector CON3 is used to extend the normal IO of the
BANK15 and BANK16 of the FPGA. In addition, four JTAG signals are also
connected to the carrier board via the CON3 connector. The voltage standards
of BANK15 and BANK16 can be adjusted by an LDO chip. The default installed
LDO is 3.3V. If you want to output other standard levels, you can replace it with
a suitable LDO.
Pin Assignment of Board to Board Connectors CON3
CON3 Net
PIN Name
PIN1 B15_IO0
PIN3 B16_IO0
PIN5 B15_L4_P
PIN7 B15_L4_N
PIN9 GND
PIN11 B15_L2_P
PIN13 B15_L2_N
PIN15 B15_L12_P
PIN17 B15_L12_N
PIN19 GND
PIN21 B15_L11_P
PIN23 B15_L11_N
PIN25 B15_L1_N
PIN27 B15_L1_P
PIN29 GND
PIN31 B15_L5_P
PIN33 B15_L5_N
PIN35 B15_L3_N
PIN37 B15_L3_P
PIN39 GND
PIN41 B15_L19_P
PIN43 B15_L19_N
28 / 59
ARTIX-7 FPGA Development Board AX7A035 User Manual
FPGA Voltage
PIN Level
J16
F15
G17
G18
- Ground
G15
G16
J19
H19
- Ground
J20
J21
G13
H13
- Ground
J15
H15
H14
J14
- Ground
K13
K14 3.3V
CON3
PIN
3.3V PIN2
3.3V PIN4
3.3V PIN6 B16_L21_N
3.3V PIN8 B16_L21_P
PIN10
3.3V PIN12 B16_L23_P
3.3V PIN14 B16_L23_N
3.3V PIN16 B16_L22_P
3.3V PIN18 B16_L22_N
PIN20
3.3V PIN22 B16_L24_P
3.3V PIN24 B16_L24_N
3.3V PIN26
3.3V PIN28
PIN30
3.3V PIN32
3.3V PIN34
3.3V PIN36
3.3V PIN38
PIN40
3.3V PIN42
PIN44
Net FPGA
Name PIN
B15_IO25 M17
B16_IO25 F21
A21
B21
GND -
E21
D21
E22
D22
GND -
G21
G22
B15_L8_N G20
B15_L8_P H20
GND -
B15_L7_N H22
B15_L7_P J22
B15_L9_P K21
B15_L9_N K22
GND -
B15_L15_N M22
B15_L15_P N22
www.alinx.com
Voltage
Level
3.3V
3.3V
3.3V
3.3V
Ground
3.3V
3.3V
3.3V
3.3V
Ground
3.3V
3.3V
3.3V
3.3V
Ground
3.3V
3.3V
3.3V
3.3V
Ground
3.3V
3.3V