Part 3.2: Gigabit Ethernet Interface - Alinx AX7A035 User Manual

Part 3.2: Gigabit Ethernet Interface

The AX7A035 FPGA development board provides users with 1-channel
Gigabit network communication service through the Micrel KSZ9031RNX
Ethernet PHY chip. The Ethernet PHY chip is connected to the IO interface of
the ARTIX7 FPGA. The KSZ9031RNX chip supports 10/100/1000 Mbps
network transmission rate and communicates with the FPGA through the
RGMII interface. KSZ9031RNX supports MDI/MDX adaptation, various speed
adaptations, Master/Slave adaptation, and support for MDIO bus for PHY
register management.
The KSZ9031RNX will detect the level status of some specific IOs to
determine their working mode after powered on. Table 3-1-1 describes the
default setup information after the GPHY chip is powered on.
Configuration Pin
PHYAD[2:0]
CLK125_EN
LED_MODE
MODE0~MODE3
When the network is connected to Gigabit Ethernet, the data
transmission of FPGA and PHY chip KSZ9031RNX is communicated through
the RGMII bus, the transmission clock is 125Mhz, and the data is sampled on
the rising and falling edge of the clock.
When the network is connected to 100M Ethernet, the data transmission of
FPGA and PHY chip KSZ9031RNX is communicated through the RMII bus, the
transmission clock is 25Mhz, and the data is sampled on the rising and falling
edge of the clock.
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ARTIX-7 FPGA Development Board AX7A035 User Manual
Instructions
MDIO/MDC Mode PHY Address
Enable 125Mhz clock output
selection
LED light mode configuration
Link adaptation and full duplex
configuration
Table 3-2-1: PHY chip default configuration value
Configuration value
PHY Address 011
Enable
Single LED light mode
10/100/1000 adaptive, compatible
Full-duplex, half-duplex
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