Alinx AX7A035 User Manual page 29

PIN45 B15_L20_P
PIN47 B15_L20_N
PIN49 GND
PIN51 B15_L14_P
PIN53 B15_L14_N
PIN55 B15_L21_P
PIN57 B15_L21_N
PIN59 GND
PIN61 B15_L23_P
PIN63 B15_L23_N
PIN65 B15_L22_P
PIN67 B15_L22_N
PIN69 GND
PIN71 B15_L24_P
PIN73 B15_L24_N
PIN75 NC
PIN77 FPGA_TCK
PIN79 FPGA_TDO
The Pin1 of the connector has been marked with a dot on the board.
Figure 2-9-3: Board to Board Connectors CON3 on the Core Board
Board to Board Connectors CON4
The 80-Pin connector CON4 is used to extend the normal IO and GTP
high-speed data and clock signals of the FPGA BANK16. The voltage standard
of the IO port of BANK16 can be adjusted by an LDO chip. The default installed
LDO is 3.3V. If the user wants to output other standard levels, it can be
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ARTIX-7 FPGA Development Board AX7A035 User Manual
M13 3.3V
L13 3.3V
- Ground
L19 3.3V
L20 3.3V
K17 3.3V
J17
- Ground
L16
K16
L14
L15
- Ground
M15
M16
-
V12
U13
PIN46
PIN48
PIN50
PIN52
PIN54
PIN56
3.3V PIN58
PIN60
3.3V PIN62
3.3V PIN64
3.3V PIN66
3.3V PIN68
PIN70
3.3V PIN72
3.3V PIN74
PIN76
3.3V PIN78
3.3V PIN80
B15_L6_N H18
B15_L6_P H17
GND -
B15_L13_N K19
B15_L13_P K18
B15_L10_P M21
B15_L10_N L21
GND -
B15_L18_P N20
B15_L18_N M20
B15_L17_N N19
B15_L17_P N18
GND -
B15_L16_P M18
B15_L16_N L18
NC -
FPGA_TDI R13
FPGA_TMS T13
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3.3V
3.3V
Ground
3.3V
3.3V
3.3V
3.3V
Ground
3.3V
3.3V
3.3V
3.3V
Ground
3.3V
3.3V
3.3V
3.3V