Alinx AX7A035 User Manual page 30

replaced by a suitable LDO. The high-speed data and clock signals of the GTP
are strictly differential routed on the core board. The data lines are equal in
length and kept at a certain interval to prevent signal interference.
Pin Assignment of Board to Board Connectors CON4
CON4 Net
PIN Name
NC
PIN1
NC
PIN3
NC
PIN5
NC
PIN7
GND
PIN9
NC
PIN11
NC
PIN13
GND
PIN15
MGT_TX3_P
PIN17
MGT_TX3_N
PIN19
GND
PIN21
MGT_RX3_P
PIN23
MGT_RX3_N
PIN25
PIN27 GND
MGT_TX1_P
PIN29
MGT_TX1_N
PIN31
GND
PIN33
MGT_RX1_P
PIN35
MGT_RX1_N
PIN37
GND
PIN39
PIN41 B16_L5_P
PIN43 B16_L5_N
PIN45 B16_L7_P
PIN47 B16_L7_N
PIN49 GND
PIN51 B16_L9_P
PIN53 B16_L9_N
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ARTIX-7 FPGA Development Board AX7A035 User Manual
FPGA Voltage
PIN Level
- -
- -
- -
- -
- Ground
- -
- -
- Ground
D7 Diff
C7 Diff
- Ground
D9 Diff
C9 Diff
- Ground
D5 Diff
C5 Diff
- Ground
D11 Diff
C11 Diff
- Ground
E16 3.3V
D16 3.3V
B15 3.3V
B16 3.3V
- Ground
A15 3.3V
A16 3.3V
CON4 Net
PIN Name
PIN2
PIN4
PIN6
PIN8
GND
PIN10
MGT_TX2_P
PIN12
MGT_TX2_N
PIN14
GND
PIN16
MGT_RX2_P
PIN18
MGT_RX2_N
PIN20
GND
PIN22
MGT_TX0_P
PIN24
MGT_TX0_N
PIN26
PIN28 GND
PIN30 MGT_RX0_P
PIN32 MGT_RX0_N
PIN34 GND
PIN36 MGT_CLK1_P
PIN38 MGT_CLK1_N
PIN40 GND
PIN42 B16_L2_P
PIN44 B16_L2_N
PIN46 B16_L3_P
PIN48 B16_L3_N
PIN50 GND
PIN52 B16_L10_P
PIN54 B16_L10_N
FPGA Voltage
PIN Level
- -
- -
- -
- -
- Ground
B6 Diff
A6 Diff
- Ground
B10 Diff
A10 Diff
- Ground
B4 Diff
A4 Diff
- Ground
B8 Diff
A8 Diff
- Ground
F10 Diff
E10 Diff
- Ground
F16 3.3V
E17 3.3V
C14 3.3V
C15 3.3V
- Ground
A13 3.3V
A14 3.3V
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