Part 2.7: Jtag Interface - Alinx AX7A035 User Manual

User LEDs Pin Assignment
Signal Name
LED1

Part 2.7: JTAG Interface

The JTAG test socket J1 is reserved on the AC7A035 core board for JTAG
download and debugging when the core board is used alone. Figure 2-7-1 is
the schematic part of the JTAG port, which involves TMS, TDI, TDO, TCK. ,
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ARTIX-7 FPGA Development Board AX7A035 User Manual
Figure 2-6-2: LED lights on the Core Board
FPGA Pin Name
IO_L15N_T2_DQS_34
FPGA Pin Number
W5
Description
User LED
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