Alinx ARTIX-7FPGA User Manual
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Alinx ARTIX-7FPGA User Manual

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ARTIX-7 FPGA
Development Board
AX7203
User Manual

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  • Page 1 ARTIX-7 FPGA Development Board AX7203 User Manual...

  • Page 2: Version Record

    ARTIX-7 FPGA Development Board AX7203 User Manual Version Record Version Date Release By Description Rev 1.2 2023-02-23 Rachel Zhou First Release 2 / 57 www.alinx.com...

  • Page 3: Table Of Contents

    Part 3.5: HDMI Input interface ............42 Part 3.6: SD Card Slot ................ 44 Part 3.7: USB to Serial Port ..............45 Part 3.8: EEPROM 24LC04 ..............47 Part 3.9: Expansion Header ............... 48 Part 3.10: JTAG Interface ..............51 3 / 57 www.alinx.com...
  • Page 4 ARTIX-7 FPGA Development Board AX7203 User Manual Part 3.11: XADC interface (not installed by default) ......52 Part 3.12: keys ..................53 Part 3.13: LED Light ................54 Part 3.14: Power Supply ..............55 4 / 57 www.alinx.com...
  • Page 5 It provides the possibility for high-speed video transmission, pre-validation and post-application of network and fiber communication and data processing. This product is very suitable for students, engineers and other groups engaged in ARTIX-7FPGA development. 5 / 57 www.alinx.com...

  • Page 6: Part 1: Fpga Development Board Introduction

    The AX7203 carrier board expands its rich peripheral interface, including 1 PCIex4 interface, 2 Gigabit Ethernet interfaces, 1 HDMI Output interface, 1 HDMI Input interface, 1 Uart Interface, 1 SD card slot, XADC connector interface, 2-way 40-pin expansion header, some keys, LED and EEPROM circuit. 6 / 57 www.alinx.com...
  • Page 7 Supports PCI Express 2.0 standard, provides PCIe x4 high-speed data transmission interface, single channel communication rate up to 5GBaud  2-channel Gigabit Ethernet Interface RJ-45 interface The Gigabit Ethernet interface chip uses Micrel's KSZ9031RNX Ethernet PHY chip to provide network communication services to users. 7 / 57 www.alinx.com...
  • Page 8  2-way 40-pin expansion port 2-way 40-pin 2.54mm pitch expansion port can be connected to various ALINX modules (binocular camera, TFT LCD screen, high-speed AD module, etc.). The expansion port contains 1 channel 5V power supply, 2 channel 3.3V power supply, 3 way ground, 34 IOs port.

  • Page 9: Part 2: Ac7200 Core Board Introduction

    For users who need a lot of IO, this core board will be a good choice. Moreover, the routing between the FPGA chip and the interface is equal length and differential processing, and the core board size is only 45*55 (mm), which is very suitable for secondary development. 9 / 57 www.alinx.com...

  • Page 10: Part 2.1: Fpga Chip

    Xilinx's Artix-7 series. The speed grade is 2, and the temperature grade is industry grade. This model is a FGG484 package with 484 pins. Xilinx ARTIX-7 FPGA chip naming rules as below The Specific Chip Model Definition of ARTIX-7 Series 10 / www.alinx.com...
  • Page 11 FPGA core power supply pin, which needs to be connected MGTAVTT CCINT to 1.0V; V is the power supply pin of FPGA block RAM, connect to 1.0V; CCBRAM is FPGA auxiliary power supply pin, connect 1.8V; V is the voltage of CCAUX 11 / www.alinx.com...

  • Page 12: Part 2.2: Active Differential Crystal

    BANK34 global clock pin MRCC (R4 and T4) of the FPGA. This 200Mhz differential clock can be used to drive the user logic in the FPGA. Users can configure the PLLs and DCMs inside the FPGA to generate clocks of different frequencies. 12 / www.alinx.com...

  • Page 13: Part 2.4: 148.5Mhz Active Differential Crystal

    G2 is the 148.5Mhz active differential crystal, which is the reference input clock provided to the GTP module inside the FPGA. The crystal output is connected to the GTP BANK216 clock pins MGTREFCLK0P (F6) and MGTREFCLK0N (E6) of the FPGA. 13 / www.alinx.com...
  • Page 14 ARTIX-7 FPGA Development Board AX7203 User Manual 148.5Mhz Active Differential Crystal Schematic 1148.5Mhz Active Differential Crystal on the Core Board 125Mhz Differential Clock Pin Assignment Net Name FPGA PIN MGT_CLK0_P MGT_CLK0_N 14 / www.alinx.com...

  • Page 15: Part 2.5: Ddr3 Dram

    The hardware design of DDR3 requires strict consideration of signal integrity. We have fully considered the matching resistor/terminal resistance, trace impedance control, and trace length control in circuit design and PCB design to ensure high-speed and stable operation of DDR3. The DDR3 DRAM Schematic 15 / www.alinx.com...
  • Page 16 FPGA PIN Name FPGA P/N DDR3_DQS0_P IO_L3P_T0_DQS_AD5P_35 DDR3_DQS0_N IO_L3N_T0_DQS_AD5N_35 DDR3_DQS1_P IO_L9P_T1_DQS_AD7P_35 DDR3_DQS1_N IO_L9N_T1_DQS_AD7N_35 DDR3_DQS2_P IO_L15P_T2_DQS_35 DDR3_DQS2_N IO_L15N_T2_DQS_35 DDR3_DQS3_P IO_L21P_T3_DQS_35 DDR3_DQS3_N IO_L21N_T3_DQS_35 DDR3_DQ[0] IO_L2P_T0_AD12P_35 DDR3_DQ [1] IO_L5P_T0_AD13P_35 DDR3_DQ [2] IO_L1N_T0_AD4N_35 DDR3_DQ [3] IO_L6P_T0_35 DDR3_DQ [4] IO_L2N_T0_AD12N_35 DDR3_DQ [5] IO_L5N_T0_AD13N_35 16 / www.alinx.com...
  • Page 17 DDR3_DQ [26] IO_L20P_T3_35 DDR3_DQ [27] IO_L22N_T3_35 DDR3_DQ [28] IO_L23P_T3_35 DDR3_DQ [29] IO_L24N_T3_35 DDR3_DQ [30] IO_L24P_T3_35 DDR3_DQ [31] IO_L22P_T3_35 DDR3_DM0 IO_L4N_T0_35 DDR3_DM1 IO_L8N_T1_AD14N_35 DDR3_DM2 IO_L16N_T2_35 DDR3_DM3 IO_L23N_T3_35 DDR3_A[0] IO_L11N_T1_SRCC_34 DDR3_A[1] IO_L8N_T1_34 DDR3_A[2] IO_L10P_T1_34 DDR3_A[3] IO_L10N_T1_34 DDR3_A[4] IO_L7N_T1_34 DDR3_A[5] IO_L6P_T0_34 17 / www.alinx.com...
  • Page 18 IO_L2N_T0_34 DDR3_A[9] IO_L2P_T0_34 DDR3_A[10] IO_L5N_T0_34 DDR3_A[11] IO_L4P_T0_34 DDR3_A[12] IO_L4N_T0_34 DDR3_A[13] IO_L1N_T0_34 DDR3_A[14] IO_L6N_T0_VREF_34 DDR3_BA[0] IO_L9N_T1_DQS_34 DDR3_BA[1] IO_L9P_T1_DQS_34 DDR3_BA[2] IO_L11P_T1_SRCC_34 DDR3_S0 IO_L8P_T1_34 DDR3_RAS IO_L12P_T1_MRCC_34 DDR3_CAS IO_L12N_T1_MRCC_34 DDR3_WE IO_L7P_T1_34 DDR3_ODT IO_L14N_T2_SRCC_34 DDR3_RESET IO_L15P_T2_DQS_34 DDR3_CLK_P IO_L3P_T0_DQS_34 DDR3_CLK_N IO_L3N_T0_DQS_34 DDR3_CKE IO_L14P_T2_SRCC_34 18 / www.alinx.com...

  • Page 19: Part 2.6: Qspi Flash

    FPGA chip. The clock pin is connected to CCLK0 of BANK0, and other data and chip select signals are connected to D00~D03 and FCS pins of BANK14 respectively. Shows the hardware connection of QSPI Flash. QSPI Flash Schematic QSPI Flash pin assignments: 19 / www.alinx.com...
  • Page 20 ARTIX-7 FPGA Development Board AX7203 User Manual Net Name FPGA PIN Name FPGA P/N QSPI_CLK CCLK_0 QSPI_CS IO_L6P_T0_FCS_B_14 QSPI_DQ0 IO_L1P_T0_D00_MOSI_14 QSPI_DQ1 IO_L1N_T0_D01_DIN_14 QSPI_DQ2 IO_L2P_T0_D02_14 QSPI_DQ3 IO_L2N_T0_D03_14 QSPI on the Core Board 20 / www.alinx.com...

  • Page 21: Part 2.7: Led Light On Core Board

    LED will be lit. The schematic diagram of the LED light hardware connection is shown: LED lights on core board Schematic LED lights on the Core Board User LEDs Pin Assignment Signal Name FPGA Pin Name FPGA Pin Number Description LED1 IO_L15N_T2_DQS_34 User LED 21 / www.alinx.com...

  • Page 22: Part 2.8: Reset Button

    IO is high. The schematic diagram of the reset button connection is shown: Reset Button Schematic Reset button on the Core Board Reset button pin assignment Signal Name ZYNQ Pin Name ZYNQ Pin Number Description RESET_N IO_L17N_T2_34 FPGA system reset 22 / www.alinx.com...

  • Page 23: Part 2.9: Jtag Interface

    If you need to use the JTAG connection to debug on the core board, you need to solder a 6-pin single-row pin header. shows the JTAG interface J1 on the AC7200 FPGA core board. JTAG Interface on Core Board 23 / www.alinx.com...

  • Page 24: Part 2.10: Power Interface On The Core Board

    2PIN power interface (J3). When the user supplies power to the core board through 2PIN power interface (J3), it cannot be powered through the carrier board. Otherwise, current conflict may occur. Power Interface on the Core Board 24 / www.alinx.com...

  • Page 25: Part 2.11: Board To Board Connectors

    Pin Assignment of Board to Board Connectors CON1 CON1 Signal Name FPGA Pin CON1 Signal Name FPGA Pin Voltage Voltage Level Level PIN1 VCCIN PIN2 VCCIN PIN3 VCCIN PIN4 VCCIN PIN5 VCCIN PIN6 VCCIN PIN7 VCCIN PIN8 VCCIN PIN9 Ground PIN10 Ground 25 / www.alinx.com...
  • Page 26 1.5V PIN55 PIN56 B34_L24_P 1.5V PIN57 PIN58 B34_L24_N 1.5V PIN59 Ground PIN60 Ground PIN61 B16_L1_N 3.3V PIN62 PIN63 B16_L1_P 3.3V PIN64 PIN65 B16_L4_N 3.3V PIN66 PIN67 B16_L4_P 3.3V PIN68 PIN69 Ground PIN70 Ground PIN71 B16_L6_N 3.3V PIN72 26 / www.alinx.com...
  • Page 27 PIN36 B14_L7_N 3.3V PIN37 B13_L8_P 3.3V PIN38 B14_L7_P 3.3V PIN39 Ground PIN40 Ground PIN41 B14_L11_N 3.3V PIN42 B14_L4_P 3.3V PIN43 B14_L11_P 3.3V PIN44 B14_L4_N 3.3V PIN45 B14_L14_N 3.3V PIN46 B14_L9_P 3.3V PIN47 B14_L14_P 3.3V PIN48 B14_L9_N 3.3V 27 / www.alinx.com...
  • Page 28 CON1 Signal Name FPGA Voltage CON1 Signal Name FPGA Pin Voltage Level Level PIN1 B15_IO0 3.3V PIN2 B15_IO25 3.3V PIN3 B16_IO0 3.3V PIN4 B16_IO25 3.3V PIN5 B15_L4_P 3.3V PIN6 B16_L21_N 3.3V PIN7 B15_L4_N 3.3V PIN8 B16_L21_P 3.3V 28 / www.alinx.com...
  • Page 29 Ground PIN60 Ground PIN61 B15_L23_P 3.3V PIN62 B15_L18_P 3.3V PIN63 B15_L23_N 3.3V PIN64 B15_L18_N 3.3V PIN65 B15_L22_P 3.3V PIN66 B15_L17_N 3.3V PIN67 B15_L22_N 3.3V PIN68 B15_L17_P 3.3V PIN69 Ground PIN70 Ground PIN71 B15_L24_P 3.3V PIN72 B15_L16_P 3.3V 29 / www.alinx.com...
  • Page 30 MGT_TX3_P Differential PIN18 MGT_RX2_P Differential PIN19 MGT_TX3_N Differential PIN20 MGT_RX2_N Differential PIN21 Ground PIN22 Ground PIN23 MGT_RX3_P Differential PIN24 MGT_TX0_P Differential PIN25 MGT_RX3_N Differential PIN26 MGT_TX0_N Differential PIN27 Ground PIN28 Ground PIN29 MGT_TX1_P Differential PIN30 MGT_RX0_P Differential 30 / www.alinx.com...
  • Page 31 3.3V PIN67 B16_L15_N 3.3V PIN68 B16_L16_N 3.3V PIN69 Ground PIN70 Ground PIN71 B16_L17_P 3.3V PIN72 B16_L18_P 3.3V PIN73 B16_L17_N 3.3V PIN74 B16_L18_N 3.3V PIN75 B16_L19_P 3.3V PIN76 B16_L20_P 3.3V PIN77 B16_L19_N 3.3V PIN78 B16_L20_N 3.3V PIN79 PIN80 31 / www.alinx.com...

  • Page 32: Part 2.12: Power Supply

    VTT and VREF voltages required by DDR3 via TI's TPS51200. The 1.8V power supply MGTAVTT MGTAVCC for the GTP transceiver is generated by TI's TPS74801 chip. The functions of each power distribution are shown in the following table: 32 / www.alinx.com...

  • Page 33: Part 2.13: Structure Diagram

    1.0V->1.8V->(1.5 V, 3.3V, VCCIO) and 1.0V-> MGTAVCC -> MGTAVTT, the circuit design to ensure the normal operation of the chip. Part 2.13: Structure Diagram 33 / www.alinx.com...

  • Page 34: Part 3: Carrier Board

     1-channel HDMI video Output interface  1-channel USB Uart Communication interface  1 SD Card Slot  XADA Interface  EEPROM  2-channel 40-pin expansion ports  JTAG debugging interface  2 independent keys  4 user LED lights 34 / www.alinx.com...

  • Page 35: Part 3.2: Gigabit Ethernet Interface

    FPGA and PHY chip KSZ9031RNX is communicated through the GMII bus, the transmission clock is 25Mhz. The receive clock E_RXC is provided by the PHY chip, the transmit clock E_GTXC is provided by the FPGA, and the data is 35 / www.alinx.com...
  • Page 36 ARTIX-7 FPGA Development Board AX7203 User Manual sampled on the rising edge of the clock. Figure 3-2-1: Gigabit Ethernet Interface Schematic Figure 3-3-2: Gigabit Ethernet interface on the Carrier board 36 / www.alinx.com...
  • Page 37 PHY2 Receive Data Bit0 E2_RXD1 PHY2 Receive Data Bit1 E2_RXD2 PHY2 Receive Data Bit2 E2_RXD3 PHY2 Receive Data Bit3 E2_RXDV PHY2 receive data valid signal E2_MDC PHY2 Management Clock E2_MDIO PHY2 Management Data E2_RESET PHY2 Reset Signal 37 / www.alinx.com...

  • Page 38: Part 3.3: Pcie X4 Interface

    The design diagram of the PCIe interface of the AX7203 FPGA development board is shown in Figure 3-3-1, where the TX transmit signal and the reference clock CLK signal are connected in AC coupled mode. Figure 3-3-1: PCIex4 schematic 38 / www.alinx.com...
  • Page 39 PCIE Channel 2 Data Transmit Positive PCIE_TX2_N PCIE Channel 2 Data Transmit Negative PCIE_TX3_P PCIE Channel 3 Data Transmit Positive PCIE_TX3_N PCIE Channel 3 Data Transmit Negative PCIE_CLK_P PCIE Reference Clock Positive PCIE_CLK_N PCIE Reference Clock Negative 39 / www.alinx.com...

  • Page 40: Part 3.4: Hdmi Output Interface

    FPGA. The SIL9134 is initialized and controlled by FPGA programming. The hardware connection of the HDMI output interface is shown in Figure 3-4-1. Figure 3-4-1: HDMI Output Schematic Figure 3-4-1: HDMI Output on the Carrier board 40 / www.alinx.com...
  • Page 41 HDMI Input Pin Assignment: Signal Name FPGA Pin 9134_nRESET 9134_CLK 9134_HS 9134_VS 9134_DE 9134_D[0] 9134_D[1] 9134_D[2] 9134_D[3] 9134_D[4] 9134_D[5] 9134_D[6] 9134_D[7] 9134_D[8] 9134_D[9] 9134_D[10] 9134_D[11] 9134_D[12] 9134_D[13] 9134_D[14] 9134_D[15] 9134_D[16] 9134_D[17] 9134_D[18] 9134_D[19] 9134_D[20] 9134_D[21] 9134_D[22] 9134_D[23] 41 / www.alinx.com...

  • Page 42: Part 3.5: Hdmi Input Interface

    The IIC configuration interface of the SIL9013 is connected to the IO of the FPGA. The SIL9013 is initialized and controlled through FPGA programming. The hardware connection of the HDMI input interface is shown in Figure 3-5-1. Figure 3-5-1: HDMI Input Schematic Figure 3-5-2: HDMI Input on the Carrier board 42 / www.alinx.com...
  • Page 43 HDMI Input Pin Assignment: Signal Name FPG Pin Number 9013_nRESET 9013_CLK 9013_HS 9013_VS 9013_DE 9013_D[0] 9013_D[1] 9013_D[2] 9013_D[3] 9013_D[4] 9013_D[5] 9013_D[6] 9013_D[7] 9013_D[8] 9013_D[9] 9013_D[10] 9013_D[11] 9013_D[12] 9013_D[13] 9013_D[14] 9013_D[15] 9013_D[16] 9013_D[17] 9013_D[18] 9013_D[19] 9013_D[20] 9013_D[21] 9013_D[22] 9013_D[23] 43 / www.alinx.com...

  • Page 44: Part 3.6: Sd Card Slot

    The SD card is a very common storage device. The extended SD card supports SPI mode and SD mode. The SD card used is a MicroSD card. The schematic diagram is shown in Figure 3-6-1. Figure 3-6-1: SD Card Schematic 44 / www.alinx.com...

  • Page 45: Part 3.7: Usb To Serial Port

    Silicon Labs CP2102GM. The USB interface uses the MINI USB interface. It can be connected to the USB port of the upper PC for serial data communication with a USB cable. The schematic diagram of the USB Uart circuit design is shown in Figure 3-7-1: 45 / www.alinx.com...
  • Page 46 Two LED indicators (LED3 and LED4) are set for the serial port signal, and the silkscreen on the PCB is TX and RX, indicating that the serial port has data transmission or reception, as shown in the following Figure 3-3-3 Figure 3-7-3: Serial Port communication LED Indicators Schematic 46 / www.alinx.com...

  • Page 47: Part 3.8: Eeprom 24Lc04

    IIC bus. The I2C signal of the EEPROM is connected to the BANK14 IO port on the FPGA side. Figure 3-8-1 below shows the design of the EEPROM Figure 3-8-1: EEPROM Schematic Figure 3-8-2: EEPROM on the Carrier board 47 / www.alinx.com...

  • Page 48: Part 3.9: Expansion Header

    Part 3.9: Expansion Header The carrier board is reserved with two 0.1inch spacing standard 40-pin expansion ports J11 and J13, which are used to connect the ALINX modules or the external circuit designed by the user. The expansion port has 40 signals, of which 1-channel 5V power supply, 2-channel 3.3 V power supply, 3-channle...
  • Page 49 Pin1 and Pin2 of the expansion port are already marked on the board. Figure 3-9-2: Expansion header J11 on the Carrier board J11 Expansion Header Pin Assignment Pin Number FPGA Pin Pin Number FPGA Pin AB10 AA10 AA11 AA15 AB15 AA16 AB16 AB17 +3.3V +3.3V 49 / www.alinx.com...
  • Page 50 The figure 3-9-4 detailed the J13 expansion port on the carrier board. The Pin1 and Pin2 of the expansion port are already marked on the board. Figure 3-9-4: Expansion header J13 on the carrier board J13 Expansion Header Pin Assignment Pin Number FPGA Pin Pin Number FPGA Pin 50 / www.alinx.com...

  • Page 51: Part 3.10: Jtag Interface

    FPGA chip caused by hot plugging, a protection diode is added to the JTAG signal to ensure that the voltage of the signal is within the range accepted by the FPGA to avoid damage of the FPGA chip. Figure 3-10-1: JTAG Interface Schematic 51 / www.alinx.com...

  • Page 52: Part 3.11: Xadc Interface (Not Installed By Default)

    VP/VN of the FPGA, and the other two pairs are differentially connected to the auxiliary analog input channels (analog channel 0 and analog channel 9). Figure 3-11-1 shows an anti-aliasing filter designed for three differential XADC inputs. Figure 3-11-1: Anti-Aliasing filter Schematic 52 / www.alinx.com...

  • Page 53: Part 3.12: Keys

    IO input voltage of the FPGA is low. When no key is pressed, The IO input voltage of the FPGA is high. The circuit of the key part is shown in Figure 3-12-1. 53 / www.alinx.com...

  • Page 54: Part 3.13: Led Light

    IO of the FPGA. When the IO voltage connected to the user LED is configured low level, the user LED lights up. When the connected IO voltage is configured as high level, the user LED will be extinguished. The 54 / www.alinx.com...

  • Page 55: Part 3.14: Power Supply

    Part 3.14: Power Supply The power input voltage of the AX7203 FPGA development board is DC12V. The development board also supports power from the PCIe interface and supports direct power supply from the ATX chassis power supply (12V). 55 / www.alinx.com...
  • Page 56 MP1482. In addition, the +5V power supply on the FPGA carrier board supplies power to the AC7100B FPGA core board through the inter-board connector. The power supply design on the expansion is shown in Figure 3-14-2. Figure 3-14-2: Power supply Schematic on the Carrier board 56 / www.alinx.com...
  • Page 57 ARTIX-7 FPGA Development Board AX7203 User Manual Figure 3-14-3: Power Supply Circuit on the Carrier board 57 / www.alinx.com...

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