Xilinx Design Constraints - AMD XILINX VEK280 User Manual

3/20/24, 12:51 PM
VITA 57.4 FMCP Connector Pinouts
Overview
The following figure shows the pinout of the FPGA plus mezzanine card (FMCP)
high pin count (HSPC) connector defined by the VITA 57.4 FMC specification. For a
description of how the VEK280 evaluation board implements the FMCP
specification, see
Figure: FMCP HSPC Connector Pinout

Xilinx Design Constraints

Overview
The Xilinx design constraints (XDC) file template for the VEK280 board provides for
designs targeting the VEK280 evaluation board. Net names in the constraints listed
correlate with net names on the latest VEK280 evaluation board schematic. Identify
the appropriate pins and replace the net names with net names in the user RTL.
See the Vivado Design Suite User Guide: Using Constraints (UG903) for more
information.
The HSPC FMCP connector J51 is connected to the AMD Versal™ device U1 banks
powered by the variable voltage VADJ_FMC. Because different FMC cards
https://docs.amd.com/internal/api/webapp/print/d54fa025-f5b0-4797-be6e-41b3e31f9548
GTYP200/201: FPGA Mezzanine Card
Unofficial Document
Interface.
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