AMD XILINX VEK280 User Manual page 47

3/20/24, 12:51 PM
ADIN1300 PHY Pin
Name
The LED functions can be repurposed with a LEDCR1 register write available via the
PHY's management data interface, MDIO/MDC.
See the ADI ADIN1300 RGMII PHY data sheet at the
component details.
The detailed device connections for the feature described in this section are
documented in the VEK280 board XDC file, referenced in
PMC MIO[11,49] and LPD MIO[12,13,20,23]: Power Enable
[Figure 1, callout 22-30]
The VEK280 allows the Versal device to control the power to the various power
domains. This is an active-High signal. It is connected to the components that are
controlled using an open-drain buffer. Signals are listed in the following table with
their associated power domains. The output of the buffers are pulled up with a 4.7K
resistor to aid in the default boot state being set properly. When J345 is installed,
the associated power enables and, consequently, power supplies are disabled. This
can be useful when changing the programmable power supply default
programming. When not installed, the Versal device shares control with
UTIL_5V0_PGOOD, which is an output from the 5.0V power supply (U191). See
schematic page 71 for more information (see
Table: PMC MIO[49] and LPD MIO[12,13,20,23] Power Domains
Versal Device Pin
https://docs.amd.com/internal/api/webapp/print/d54fa025-f5b0-4797-be6e-41b3e31f9548
Number
The LED_0 can be used to indicate the speed of
operation, link status, and duplex mode.
By default, LED_0 illuminates when a link is
established and blinks when there is activity. The
default LED operation can be overwritten in
software using the PHY LED control registers,
LED_CTRL_1, LED_CTRL_2, and LED_CTRL_3
(Register Address 0x001B, Register Address
0x001C, and Register Address 0x001D,
respectively).
Signal
Unofficial Document
Description
Analog Devices
Xilinx Design
Jumpers for defaults).
Power Domains
website for
Constraints.
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