AMD XILINX VEK280 User Manual page 22

3/20/24, 12:51 PM
Boot Mode
SD1 (SD 3.0)
1. Default switch setting.
2. Mode DIP SW1 poles [1:4] correspond to U1 XCVE2802 MODE[0:3].
3. Mode DIP SW1 individual switches ON=LOW (p/d to GND)=0, OFF=HIGH
(p/u to VCCO)=1.
JTAG
The AMD Vivado™ , AMD SDK, or third-party tools can establish a JTAG connection
to the Versal device in the two ways described in this section.
FTDI FT4232 USB-to-JTAG/USB-UART device (U20) connected to USB 2.0 type-
C connector (J369), which requires:
Set boot mode SW1 for JTAG as indicated in the "Mode Switch SW1
Configuration Option Settings" table in
On the 3-pin JTAG MUX, enable header J37 to enable the JTAG MUX.
Move the 2-pin jumper to be installed on pins 2-3. See
and Switch Settings
location.
Set 2-pole DIP SW3[1:2] set to 10 (OFF, ON) for JTAG MUX channel 2
FT4232 U20 bridge.
Power-cycle the VEK280 evaluation board or press the power-on reset
(POR) pushbutton (SW2). SW2 is near the USB-C JTAG port J369 in the
figure in
https://docs.amd.com/internal/api/webapp/print/d54fa025-f5b0-4797-be6e-41b3e31f9548
Mode Pins [0:3]
0111
for defaults and
Board Component
Unofficial Document
2
Versal Device
Board Component Location
Location).
Mode SW1 [1:4]
ON, OFF, OFF, OFF
Configuration.
Default Jumper
for
2
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