AMD XILINX VEK280 User Manual page 27

3/20/24, 12:51 PM
Versal Device (U1) Bank
XPIO Bank
707
XPIO Bank
708
XPIO Bank
400
XPIO Bank
401
PMC MIO
500
PMC MIO
501
LPD MIO
502
1. The VEK280 board is shipped with VADJ_FMC set to 1.5V. This value
cannot be changed. Care must be taken when using FMC accessories.
See LPD MIO[23]: VADJ_FMC Power Rail
LPDDR4 Component Memory
[Figure 1, callout 2, 3, 4]
The VEK280 XCVE2802 device PL DDR memory interface performance is
documented in the Versal Premium Series Data Sheet: DC and AC Switching
https://docs.amd.com/internal/api/webapp/print/d54fa025-f5b0-4797-be6e-41b3e31f9548
Power Supply Rail Net Name Voltage
VCC1V1_LP4 1.1V
VCC1V1_LP4 1.1V
VCCO_HDIO_3V3 3.3V
(default)
VCCO_HDIO_3V3 3.3V
(default)
VCCO_MIO 1.8V
VCCO_MIO 1.8V
VCCO_502 1.8V
Unofficial Document
Description
FMCP1_LA[19:33],
FMCP1_CLK1_M2C
LPDDR4 TRIP3 CH1
LPDDR4 TRIP3 CH0
PL_GEM0 MDIO/MDC,
PMOD_IO[0:7], PL_GEM0_RX/TX
PL_GEM1_MDIO/MDC,
PL_GEM[0:1]_RST, SFP_TX_FAULT,
SFP_RX_LOS, UART1_TXD/RXD,
SYSCTLR_UART0, PL_GEM1_RX/TX
SYSMON, USB ULPI 2.0 interface,
OSPI interface
SD bus power, PCIe controls,
I2C0/21, UART0, CAN0_nSTB,
System Controller I2C/[trigger OR
CANFD0_INH], SD card controls,
GEM reset
GEM interface/controls, power
enables, PCIe PERST, fan tach, fan
PWM
for more details.
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