AMD XILINX VEK280 User Manual page 52

3/20/24, 12:51 PM
The VEK280 evaluation board has one I2C programmable RC21008A high-
performance frequency synthesizer (U299) that provides excellent phase jitter on
reference clocks. The output has been configured in various outputs. See the Clock
Sources table in the
At power-up, this clock defaults to an output frequency of 200 MHz for the LPDDR4,
100 MHz for the transceivers attached to the FMC+, 156.25 MHz for the
transceivers attached to the zSFP+, and 25 MHz for the onboard Ethernet. User
applications or the system controller can change the output frequency within the
range of 0.001 MHz to 650 MHz through the I2C bus interface. Power cycling the
VEK280 evaluation board reverts this user clock to the default frequencies listed
previously.
Programmable frequency synthesizer: Renesas RC21008A097#BB0
0.001 MHz-650 MHz range, 156.25 MHz default
I2C address 0x09
LVDS differential output
Fixed HSDP REF Clock
[Figure 1, callout 45]
The VEK280 evaluation board has a fixed frequency very low jitter 3.3V LVDS
oscillator (U374). The 156.25 MHz HSDP_156_25_REFCLK clock signal is
connected to the XCVE2802 device U1 bank 106. At power-up, this clock defaults to
an output frequency of 156.25 MHz.
Fixed oscillator: CTS 626L15625I3T
156.25 MHz default
LVDS differential output, total stability: ±25 ppm
Transceivers
The Versal device has 32 PL GTYP transceivers. The following table contains the
mapping to hardened features, quads, channel locations, as well as general
features.
Table: Transceiver Mapping
FMC+ FMCP1_DP4 CH0 GTYP
https://docs.amd.com/internal/api/webapp/print/d54fa025-f5b0-4797-be6e-41b3e31f9548
Clock Generation section for more details.
XCVE2802
PCIe
Quad X1Y2
Unofficial Document
PCIe GTYP CH0 Versal_HSDP
X0Y2 Quad
HSDP/
SFP28
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