AMD XILINX VEK280 User Manual page 51

3/20/24, 12:51 PM
Ref. Des.
U299 DDR4 DIMM CLK, 200 MHz, 3.3V LVDS,
0x09
U299 DDR4 DIMM CLK, 200 MHz, 3.3V LVDS,
0x09
U299 Adaptive SoC U1 GTYP (FMC+) CLK, 100
MHz, 3.3V LVDS, 0x09
U299 Adaptive SoC U1 GTYP (FMC+) CLK, 100
MHz, 3.3V LVDS, 0x09
U299 Adaptive SoC U1 GTYP (zSFP+) CLK,
156.25 MHz, 3.3V LVDS, 0x09
U299 Adaptive SoC U1 processing system (PS)
reference CLK, 33.33 MHz, 1.8V
LVCMOS, 0x09
U299 Master mode Ethernet CLK, 25 MHz,
1.8V LVCMOS, 0x09
U374 Adaptive SoC U1 HSDP CLK, 156.25
MHz, 3.3V LVDS
U344 HDMI RX RCLK, various, 3.3V differential,
0x5B
U344 HDMI RX OUT CLK, various, 3.3V
differential, 0x5B
U1 IEEE-1588 eCPRI CLK, various, 3.3V, 0x5B
The detailed device connections for the feature described in this section are
documented in the VEK280 board XDC file, referenced in
Programmable MGT RC21008A REF Clocks
[Figure 1, callout 36]
https://docs.amd.com/internal/api/webapp/print/d54fa025-f5b0-4797-be6e-41b3e31f9548
Feature
Unofficial Document
Notes
Renesas output 2
RC21008A
Renesas output 3
RC21008A
Renesas output 6
RC21008A
Renesas output 7
RC21008A
Renesas output 8
RC21008A
Renesas output
10
RC21008A
Renesas output
11
RC21008A
CTS
626L15625I3T
TI
TMDS1204
TI
TMDS1204
Adaptive SoC
XCVE2802
Xilinx Design
Schematic Page
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3, 92
Constraints.
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