AMD XILINX VEK280 User Manual page 7

3/20/24, 12:51 PM
Not used (1, bank GTYP106)
System controller HSDP (1, banks GTYP106)
USB-C HSDP (1, banks GTYP106)
SFP28 (1, bank GTYP106)
PCIe Gen 4 (16, banks GTYP102-GTYP105)
FMCP1 HSPC DP (8, banks GTYP205, GTYP206)
PS PMC MIO connectivity
PS MIO[0:12]: boot configuration OSPI
PS MIO[13:25]: USB2.0
PS MIO[26:36, 51]: SD1 I/F
PS MIO[37]: ZU4_TRIGGER/CANFD0_INH (J406)
PS MIO[38]: CAN0_nSTB
PS MIO[39:41]: SYSMON_I2C
PS MIO[42:43]: UART0 to FTDI
PS MIO[44:47]: I2C1, I2C0
PS MIO[48], PS LPD MIO[0:11, 24:25]: GEM0 RGMII Ethernet RJ-45
PS MIO[11,49] and LPD MIO[12,13,20,23]: power enables
PS MIO[50] and LPD MIO[18:19]: PCIe status
PS LPD MIO [21:22]: optional fan interface
LPD MIO[23]: VADJ_FMC power rail
Security: PSBATT button battery backup
SYSMON header
Operational switches (power on/off, POR_B, boot mode DIP switch)
Operational status LEDs (INIT, DONE, PS STATUS, PGOOD)
See
Power management
System controller (XCZU4EG)
The VEK280 evaluation board provides a rapid prototyping platform using the
XCVE2802-2MSEVSVH device. See the Versal Architecture and Product Data Sheet:
Overview (DS950) for a feature set overview, description, and ordering information.
https://docs.amd.com/internal/api/webapp/print/d54fa025-f5b0-4797-be6e-41b3e31f9548
Power and Status LEDs
Unofficial Document
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