AMD XILINX VEK280 User Manual page 30

3/20/24, 12:51 PM
PMC and LPD MIO
The following sections provide the MIO peripheral mapping implemented on the
VEK280 evaluation board. See the Versal Adaptive SoC Technical Reference Manual
(AM011) for more information on MIO peripheral mapping. Additional signal
connectivity can be located in the following schematic sections:
Bank 500: See schematic page 10
Bank 501: See schematic page 10
Bank 502: See schematic page 11
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