AMD XILINX VEK280 User Manual page 31

3/20/24, 12:51 PM
The following table provides MIO peripheral mapping implemented on the VEK280
evaluation board. The Versal device bank 500, 501, and 502 mappings are listed in
the following table.
Table: MIO Peripheral Mapping
Bank MIO #
500 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
https://docs.amd.com/internal/api/webapp/print/d54fa025-f5b0-4797-be6e-41b3e31f9548
Device
OSPI PMC_MIO0_OSPI_CLK
PMC_MIO1_OSPI_DQ0
PMC_MIO2_OSPI_DQ1
PMC_MIO3_OSPI_DQ2
PMC_MIO4_OSPI_DQ3
PMC_MIO5_OSPI_DQ4
PMC_MIO6_OSPI_DQS
PMC_MIO7_OSPI_DQ5
PMC_MIO8_OSPI_DQ6
PMC_MIO9_OSPI_DQ7
PMC_MIO10_OSPI0_CS_BO
Regulator PMC_MIO11_VCC_AUX_1V2_EN
Enable
GPIO
OSPI PMC_MIO12_OSPI_RST_BO
USB PMC_MIO13_USB_RST_B O
PMC_MIO14_USB_DAT0 I/O
PMC_MIO15_USB_DAT1 I/O
PMC_MIO16_USB_DAT2 I/O
PMC_MIO17_USB_DAT3 I/O
Unofficial Document
Signal I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Notes
See Table 1
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