AMD XILINX VEK280 User Manual page 33

3/20/24, 12:51 PM
Bank MIO #
39
40
41
42
43
44
45
46
47
48
49
50
51
502 0
1
2
3
4
5
6
https://docs.amd.com/internal/api/webapp/print/d54fa025-f5b0-4797-be6e-41b3e31f9548
Device
See CAN
Interface
SYSMON PMC_MIO39_SYSMON_I2C_SCL
I2C
PMC_MIO40_SYSMON_I2C_SDA
PMC_MIO41_SYSMON_I2C_ALERT
UART PMC_MIO42_501_RX_IN I
PMC_MIO43_501_TX_OUT O
I2C1 PMC_MIO44_501_LP_I2C1_SCL
PMC_MIO45_501_LP_I2C1_SDA
I2C0 PMC_MIO46_501_I2C0_SCL
PMC_MIO47_501_I2C0_SDA
GEM0 PMC_MIO48_GEM_RST_BO
Regulator PMC_MIO49_VCC_PSLP_EN
Enable
GPIO
PCIe PMC_MIO50_PCIE_WAKE_B O
SD PMC_MIO51_SD_BUSPWR O
GEM0 LPD_MIO0_GEM_TX_CLK O
LPD_MIO1_GEM_TX_D0 I/O
LPD_MIO2_GEM_TX_D1 I/O
LPD_MIO3_GEM_TX_D2 I/O
LPD_MIO4_GEM_TX_D3 I/O
LPD_MIO5_GEM_TX_CTL I/O
LPD_MIO6_GEM_RX_CLK I
Unofficial Document
Signal I/O
O
I/O
I/O
O
O
I/O
I/O
O
Notes
See Table 1
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