AMD XILINX VEK280 User Manual page 49

3/20/24, 12:51 PM
possible experience, in the case of the VEK280 evaluation and prototyping board, a
compromise had to be made. Due to the I/O limitations on the XCVE2802-
2MSEVSVH1760 package, there is limited VITA 57.4 compatibility. As the targeted
use case for the VEK280 requires LPDDR4, a large quantity of I/O pins is used for
the memory. This prevents the use of other features and capabilities for the
designated feature set. To resolve this, pin-efficient layout and routing was selected
for use with the LPDDR4. As a result, Banks 705 and 706 are tied to VADJ_FMC.
VADJ_FMC_BUS is the non-adjustable voltage for the FMC connector (J51).
VADJ_FMC and VADJ_FMC_BUS for the VEK280 is fixed to 1.5V at boot and,
consequently, is non-compliant to the VITA 57.4 FMC+ Industry Standard. The
power control of the VADJ_FMC power rail is managed by the power good and
enable connection to U282.
✎
Note: While banks 705 and 706 can be power monitored by an INA226 (U281),
the J51 VADJ pins are not monitored
JTAG Chain
[Figure 1, callout 6, 9,
The JTAG chain includes:
J36 2x7 2 mm shrouded, keyed JTAG pod flat cable connector
J369 USB3 type-C connector connected to U20 FT4232HL USB-JTAG bridge
U125 XCZU4EG System Controller bank 44
Figure: JTAG Chain Block Diagram
https://docs.amd.com/internal/api/webapp/print/d54fa025-f5b0-4797-be6e-41b3e31f9548
Figure 1, callout 14, 16]
Unofficial Document
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