AMD XILINX VEK280 User Manual page 54

3/20/24, 12:51 PM
https://docs.amd.com/internal/api/webapp/print/d54fa025-f5b0-4797-be6e-41b3e31f9548
XCVE2802
VDU PCIe
X1Y0
VDU MRMAC
X0Y0
VDU HDIO
Bank
401 AA
VDU HDIO
Bank
400 AB
Unofficial Document
GTYP CH0 PCIe
(CPM5)
Quad
CH1 PCIe
103
X0Y1
BB [RS]
CH2 PCIe
CH3 PCIe
REF0PCIe_CLK2
REF1[UNUSED]
GTYP CH0 PCIe
(CPM5)
Quad
CH1 PCIe
102
X0Y0
BA [RS]
CH2 PCIe
CH3 PCIe
REF0PCIe_CLK3
REF1[UNUSED]
PMCDIO LPDMIO
Bank Bank
503 502
PMCMIO PMCMIO/PMCDIO
Bank Bank
501 500
Lane11
Lane10
Lane9
Lane8
Lane15
Lane14
Lane13
Lane12
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