AMD XILINX VEK280 User Manual page 55

3/20/24, 12:51 PM
GTYP Transceivers
[Figure 1, callout 1]
The Versal device (U1) bank 205 and bank 206 GTYP transceivers are wired to the
FMCP connector (J51). See schematic pages 9 and 30 for details.
The GTY/GTYP transceivers in the Versal architecture are power-efficient
transceivers, supporting line rates from 1.25 Gbps to 32.75 Gbps. The GTY/GTYP
transceivers are highly configurable and tightly integrated with the programmable
logic resources of the Versal architecture. For more information, see the Versal
Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002).
GTYP102/103/104/105: PCI Express Card Edge Connectivity
For additional information about the Versal device PCIe functionality, see the Versal
Adaptive SoC CPM Mode for PCI Express Product Guide (PG346) and Versal
Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347).
Additional information about the PCI Express standard is available on the
website. See the Versal Architecture and Product Data Sheet: Overview (DS950) for
more information about this feature.
See schematic pages 7 and 40, as well as the
more details on connectivity. See schematic page 49 for details on the clocking
configuration.
GTYP200/201: FPGA Mezzanine Card Interface
[Figure 1, callout 20]
Warning: The VEK280 board can only be used with FMC cards that can support
1.5V. The VEK280 board exposes FMC add-on cards requiring lower than 1.5V
levels to this higher voltage. See
The detailed Versal device connections for the feature described in this section are
documented in the VEK280 board XDC file, referenced in
FMC+ Connector Type
The Samtec SEAF series 1.27 mm (0.050 in) pitch mates with the SEAM series
connector. For more information about the SEAF series connectors, see the
Inc. website. The 560-pin FMC+ connector defined by the FMC specification (see
VITA 57.4 FMCP Connector
https://docs.amd.com/internal/api/webapp/print/d54fa025-f5b0-4797-be6e-41b3e31f9548
Unofficial Document
VEK280 Evaluation Board
LPD MIO[23]: VADJ_FMC Power
Pinouts) provides connectivity for up to:
PCI-SIG
website for
Rail.
Xilinx Design Constraints.
Samtec,
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