AMD XILINX VEK280 User Manual page 63

3/20/24, 12:51 PM
Signal Name
SFP_TX_FAULT
SFP_TX_DISABLE U1 to module - transmitter
SFP_MOD_ABS
SFP_RX_LOS
High-speed Debug Port
The PS includes an integrated Aurora 64B/66B block that is dedicated for
accessing the debug packet controller (DPC) via a high-speed GT-based interface.
This protocol to access the DPC is the high-speed debug port (HSDP) protocol. The
HSDP provides bidirectional access to the device from an external host debug/trace
module, allowing for high-speed debug and trace operations. The SmartLynq+
module can be connected to the Aurora interface to access the HSDP in the Versal
device. For more information, see the SmartLynq+ Module User Guide (UG1514). For
information on the HSDP quad availability, see the Versal Adaptive SoC Technical
Reference Manual (AM011)).
✎
Note: The VEK280 evaluation board has additional HSDP lanes provided for
future System Controller use.
✎
Note: The integrated HSDP Aurora interface is not available in all Versal devices,
which might support HSDP using a soft Aurora solution. This interface requires
additional configuration in the Control, Interfaces, and Processing (CIPS) IP, a PL
aurora implementation, and the use of additional gigabit transceivers.
User I/O
[Figure 1, callout 17, 18 and
See Switches
The following table lists the net names, reference designators, and schematic
pages for the user I/O.
https://docs.amd.com/internal/api/webapp/print/d54fa025-f5b0-4797-be6e-41b3e31f9548
Feature
Module to U1 - fault condition
detected
disable
Logic High when module absent
Module to U1 - RX signal loss
Figure
for default values.
Unofficial Document
1, callout 41]
Notes Schematic Page
U1 Bank 401
U233 I2C
GPIO
expander
U233 I2C
GPIO
expander
U1 Bank 401
6, 29
29, 39
29, 39
6, 29
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