AMD XILINX VEK280 User Manual page 28

3/20/24, 12:51 PM
Characteristics (DS959). The VEK280 board LPDDR4 component memory interfaces
adhere to the constraints guidelines documented in the "PCB guidelines for Memory
Interfaces" section of the Versal Adaptive SoC PCB Design User Guide (UG863). The
VEK280 DDR4 component interface is a 40Ω impedance implementation. Other
memory interface details are also available in the Versal Adaptive SoC Memory
Resources Architecture Manual (AM007). For more memory component details, see
the Micron MT53E512M32D1ZW data sheet on the
current part number, see the Bill of Materials (BOM) located on the
Evaluation Board
described in this section are documented in the VEK280 board XDC file, referenced
in Xilinx Design
The VEK280 evaluation board hosts three LPDDR4 memory systems, each with a
component configuration of 2x (1x32-bit component).
Figure: LPDDR4 Component Memory
XCVE2802 U1 has been configured with three triplet banks.
XPIO triplet 1 (banks 700/701/702)
XPIO triplet 2 (banks 703/704/705)
XPIO triplet 3 (banks 706/707/708)
Each support two independent 32-bit 2 GB component interfaces (4 GB per triplet).
The VEK280 evaluation board uses the LPDDR4 memory components as follows:
https://docs.amd.com/internal/api/webapp/print/d54fa025-f5b0-4797-be6e-41b3e31f9548
website. The detailed device connections for the feature
Constraints.
Unofficial Document
Micron website. For the most
VEK280
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