Quectel QuecOpen AG525R-GL Hardware Design
  1. Manuals
  2. Brands
  3. Quectel Manuals
  4. Control Unit
  5. QuecOpen AG525R-GL
  6. Hardware design
Quectel QuecOpen AG525R-GL Hardware Design

Quectel QuecOpen AG525R-GL Hardware Design

Automotive module series
Hide thumbs
Table of Contents

Advertisement

Quick Links

AG525R-GL
Hardware Design
Automotive Module Series
Version: 1.0.0
Date: 2020-10-13
Status: Preliminary
QuecOpen
www.quectel.com

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the QuecOpen AG525R-GL and is the answer not in the manual?

Questions and answers

Related Manuals for Quectel QuecOpen AG525R-GL

Summary of Contents for Quectel QuecOpen AG525R-GL

  • Page 1 AG525R-GL QuecOpen Hardware Design Automotive Module Series Version: 1.0.0 Date: 2020-10-13 Status: Preliminary www.quectel.com...
  • Page 2 To the maximum extent permitted by law, Quectel excludes all liability for any loss or damage suffered in connection with the use of the functions and features under development, regardless of whether such loss or damage may have been foreseeable.
  • Page 3 AG525R-GL QuecOpen Hardware Design Copyright The information contained here is proprietary technical information of Quectel Wireless Solutions Co., Ltd. Transmitting, reproducing, disseminating and editing this document as well as using the content without permission are forbidden. Offenders will be held liable for payment of damages. All rights are reserved in the event of a patent grant or registration of a utility model or design.

  • Page 4: About The Document

    Automotive Module Series AG525R-GL QuecOpen Hardware Design About the Document Revision History Version Date Author Description Leon HUANG/ 2020-04-04 Alex ZHANG/ Creation of the document Evan SHEN/ Leon HUANG/ Alex ZHANG/ 2020-10-13 Preliminary Evan SHEN/ Thomas ZHANG AG525R-GL_QuecOpen_Hardware_Design 3 / 104...

  • Page 5: Table Of Contents

    Automotive Module Series AG525R-GL QuecOpen Hardware Design Contents About the Document ..........................3  Contents ..............................4  Table Index ............................... 6  Figure Index .............................. 8  1  Introduction ............................. 10  1.1.  Safety Information ........................13  2  Product Concept ..........................14  2.1.  General Description ........................ 14 ...
  • Page 6 Automotive Module Series AG525R-GL QuecOpen Hardware Design 3.13.  SDIO Interface ........................58  3.14.  SPI Interfaces ......................... 60  3.15.  RGMII Interface ........................61  3.16.  WLAN and BT Interfaces* ...................... 64  3.17.  ADC Interfaces ........................67  3.18.  USB_BOOT Interface ......................68  3.19.  GPIO Interfaces ........................
  • Page 7 Automotive Module Series AG525R-GL QuecOpen Hardware Design Table Index ® Table 1: Frequency Bands of AG525R-GL QuecOpen Module .............. 14 Table 2: Key Features ..........................17 Table 3: I/O Parameters Definition ......................23 Table 4: Pin Description ........................... 24 Table 5: Alternate Functions of Multiplexing Pins ..................35 Table 6: Overview of Operating Modes ....................
  • Page 8 Automotive Module Series AG525R-GL QuecOpen Hardware Design Table 42: GPRS Multi-slot Classes ......................104 Table 43: EDGE Modulation and Coding Schemes ................106 AG525R-GL_QuecOpen_Hardware_Design 7 / 104...
  • Page 9 Automotive Module Series AG525R-GL QuecOpen Hardware Design Figure Index ® Figure 1: Functional Diagram for AG525R-GL QuecOpen ..............20 Figure 2: Pin Assignment (Top View) ....................... 22 Figure 3: Sleep Mode Current Consumption Diagram ................40 Figure 4: Sleep Mode Application with USB Remote Wakeup ..............40 Figure 5: Sleep Mode Application without USB Remote Wakeup ............
  • Page 10 Automotive Module Series AG525R-GL QuecOpen Hardware Design Figure 42: Top View of the Module ......................94 Figure 43: Bottom View of the Module ....................94 Figure 44: Recommended Reflow Soldering Thermal Profile ..............96 Figure 45: Tape Specifications ......................... 98 Figure 46: Reel Specifications .........................

  • Page 11: Introduction

    Automotive Module Series AG525R-GL QuecOpen Hardware Design Introduction ® QuecOpen is an application solution where the module acts as a main processor. With the development of communication technology and the ever-changing market demands, more and more customers have ® realized the advantages of QuecOpen solution.
  • Page 12 Automotive Module Series AG525R-GL QuecOpen Hardware Design ❒WCDMA IV/ LTE Band 4/66:≤5.000dBi ❒WCDMA V/ LTE Band 5:≤9.416dBi ❒LTE Band 12:≤8.734dBi ❒LTE Band 13:≤9.173dBi ❒LTE Band 26:≤9.337dBi ❒LTE Band 71:≤8.447dBi 5. This module must not transmit simultaneously with any other antenna or transmitter 6.
  • Page 13 Automotive Module Series AG525R-GL QuecOpen Hardware Design IRSS-GEN "This device complies with Industry Canada’s licence-exempt RSSs. Operation is subject to the following two conditions: (1) This device may not cause interference; and (2) This device must accept any interference, including interference that may cause undesired operation of the device." or "Le présent appareil est conforme aux CNR d’Industrie Canada applicables aux appareils radio exempts de licence.

  • Page 14: Safety Information

    Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers’ failure to comply with these precautions.

  • Page 15: Product Concept

    Automotive Module Series AG525R-GL QuecOpen Hardware Design Product Concept 2.1. General Description AG525R-GL QuecOpen module is a baseband processor platform based on ARM Cortex A7 kernel. The maximum dominant frequency is up to 1.497 GHz. AG525R-GL QuecOpen module is a series of automotive-grade LTE-FDD/LTE-TDD/WCDMA/GSM wireless communication modules with receive diversity.
  • Page 16 Automotive Module Series AG525R-GL QuecOpen Hardware Design B21+B28 B25+B25/B26 B28+B38/B40/B41/B28 B29+B30/B66 B2+B12/B13/B29/B2/B30/B4/B5/B66/B71/B7 B30+B66 B34+B41 B38+B38 B39+B41/B39 B3+B18/B19/B20/B28/B38/B3/B40/B41/B5/B7/B8 B40+B40 B41+B41 B4+B12/B13/B29/B30/B4/B5/B71/B7 B5+B25/B30/B38/B40/B41/B5/B66/B7 B66+B66/B71 B7+B12/B20/B28/B32/B66/B7/B8 B8+B11/B32/B38/B39/B40/B41/B8 B12+B66+B66 B12+B12+B66 B13+B66+B66 B1+B1+B28/B3/B5/B7/B41/B8 B1+B3+B18/B19/B20/B28/B38/B3/B40/B41/B5/B7/B8 B1+B40+B40 B1+B41+B41 B1+B5+B40/B7 B1+B7+B20/B28/B7/B8 B1+B8+B38/B40 B20+B38+B38 B20+B40+B40 B25+B25+B25/B2 3CA (DL) B28+B40+B40 B28+B41+B41 B29+B30+B66 B29+B66+B66...
  • Page 17 Automotive Module Series AG525R-GL QuecOpen Hardware Design B39+B41+B4 B39+B39+B41 B3+B28+B40/B41 B3+B3+B20/B28/B41/B7/B8/B38/B40/B5 B3+B40+B40 B3+B41+B41 B3+B5+B40/B7 B3+B7+B20/B28/B7/B8 B3+B8+B38/B40 B40+B40+B40 B41+B41+B41 B4+B12+B12/B30 B4+B29+B30 B4+B4+B12/B13/B29/B30/B5/B71/B7 B4+B5+B30/B5 B4+B7+B12/B7 B5+B30+B66 B5+B40+B40 B5+B5+B66/B30 B5+B66+B66 B5+B7+B7 B66+B66+B66/B71 B7+B12+B66/B12 B7+B20+B32 B7+B66+B66 B7+B7+B8/B28/B20/B66 B8+B39+B39 B8+B40+B40 B8+B41+B41 B8+B8+B39/B41 WCDMA B1/B2/B3/B4/B5/B8/B19 (with Rx-diversity) 850/900/1800/1900 MHz GNSS Optional...

  • Page 18: Key Features

    Automotive Module Series AG525R-GL QuecOpen Hardware Design 2.2. Key Features The following table describes detailed features of the module. Table 2: Key Features Feature Details VBAT_BB/VBAT_RF: Power Supply  Supply voltage: 3.3–4.3 V  Typical supply voltage: 3.8 V  Class 4 (33 dBm ±2 dB) for GSM850/EGSM900 ...
  • Page 19 Automotive Module Series AG525R-GL QuecOpen Hardware Design  Text and PDU modes  Point to point MO and MT  SMS cell broadcast  SMS storage: ME by default (U)SIM Interfaces Support USIM/SIM card: 1.8/3.0 V  Provide one digital audio interface: I2S interface ...

  • Page 20: Functional Diagram

    Automotive Module Series AG525R-GL QuecOpen Hardware Design Rx-diversity Support LTE/WCDMA Rx-diversity  Main antenna interface (ANT_MAIN) Antenna Interfaces  Rx-diversity antenna interface (ANT_DIV)  Dimensions: (38.0 ±0.2) mm × (42.0 ±0.2) mm × (2.65 ±0.2) mm Physical Characteristics  Weight: approx. 9.23 g ...

  • Page 21: Evaluation Board

    Figure 1: Functional Diagram for AG525R-GL QuecOpen 2.4. Evaluation Board To help you develop applications conveniently with the module, Quectel supplies the evaluation board (EVB), USB data cables, a pair of earphones, antennas and other peripherals to control or test the module.

  • Page 22: Application Interfaces

    Automotive Module Series AG525R-GL QuecOpen Hardware Design Application Interfaces 3.1. General Description The module is designed with 400 LGA pins that can be connected to cellular application platforms. Module interfaces are described in detail in the following sub-chapters:  Power supply ...

  • Page 23: Pin Assignment

    Automotive Module Series AG525R-GL QuecOpen Hardware Design 3.2. Pin Assignment RES ERVED RES ERVED RES ERVED RES ERVED RES ERVED RES ERVED SPI 1 _MOSI SPI1_CS RES ERVED RES ERVED SPI1_CL K RES ERVED GPIO 5 SPI 1 _MISO WL AN_PW R_EN1 RES ERVED RES ERVED VBA T_RF...

  • Page 24: Pin Description

    Automotive Module Series AG525R-GL QuecOpen Hardware Design NOTES Keep all RESERVED pins and unused pins unconnected. GND pins should be connected to ground in the design. 3.3. Pin Description The following tables show the pin definition of the module and the alternate functions of multiplexing pins. Table 3: I/O Parameters Definition Type Description...
  • Page 25 Automotive Module Series AG525R-GL QuecOpen Hardware Design Table 4: Pin Description Power Supply Pin Name Pin No. Description Comment Characteristics Power supply for Vmax = 4.3 V It must be provided 241, 242, VBAT_BB the module’s Vmin = 3.3 V with sufficient current baseband part Vnorm = 3.8 V...
  • Page 26 Automotive Module Series AG525R-GL QuecOpen Hardware Design If unused, keep it open. For 3.0 V (U)SIM: Vmax = 3.05 V Vmin = 2.7 V For 1.8 V (U)SIM: max = 0.36 V min = 1.26 V max = 0.4 V min = 1.44 V If unused, keep it USIM1_DATA...
  • Page 27 Automotive Module Series AG525R-GL QuecOpen Hardware Design min = 1.26 V max = 0.4 V min = 1.44 V For 3.0 V (U)SIM: max = 0.57 V min = 2.0 V max = 0.4 V min = 2.28 V For 1.8 V (U)SIM: max = 0.4 V min = 1.44 V If unused, keep it...
  • Page 28 Automotive Module Series AG525R-GL QuecOpen Hardware Design transmit (-) USB 3.0 USB_SS_RX_ super-speed receive (+) USB 3.0 USB_SS_RX_ super-speed receive (-) GPIO Interfaces Pin Name Pin No. Description Comment Characteristics General-purpose GPIO1 input/output General-purpose GPIO2 input/output General-purpose GPIO3 min = -0.3 V input/output max = 0.63 V General-purpose...
  • Page 29 Automotive Module Series AG525R-GL QuecOpen Hardware Design send min = 1.35 V Can be configured to GPIOs. min = -0.3 V If unused, keep UART1 request to max = 0.63 V them open. UART1_RTS send min = 1.17 V max = 2.1 V max = 0.45 V UART1_TXD UART1 transmit...
  • Page 30 Automotive Module Series AG525R-GL QuecOpen Hardware Design resistor is required. 1.8 V only. Can be configured I2C1_SDA I2C1 serial data to GPIO. If unused, keep them open. I2S Interface (for Codec Configuration by Default) Pin Name Pin No. Description Comment Characteristics max = 0.45 V CDC_RST...
  • Page 31 Automotive Module Series AG525R-GL QuecOpen Hardware Design min = -0.3 V max = 0.63 V PCM_IN PCM data input min = 1.17 V max = 2.1 V max = 0.45 V PCM_OUT PCM data output min = 1.35 V PCIe Interface Pin Name Pin No.
  • Page 32 Automotive Module Series AG525R-GL QuecOpen Hardware Design RGMII receive data RGMII_RX_1 bit 1 RGMII receive RGMII_CTL_RX 15 control RGMII receive data RGMII_RX_2 bit 2 RGMII receive data RGMII_RX_3 bit 3 RGMII_CK_RX RGMII receive clock RGMII transmit data RGMII_TX_0 bit 0 RGMII transmit RGMII_CTL_TX 21 control...
  • Page 33 Automotive Module Series AG525R-GL QuecOpen Hardware Design SDC1_DATA_0 SDIO data bit 0 max = 0.45 V 1.8 V power domain SDC1_DATA_1 SDIO data bit 1 min = 1.4 V for eMMC min = -0.3 V SDC1_DATA_2 SDIO data bit 2 applications.
  • Page 34 Automotive Module Series AG525R-GL QuecOpen Hardware Design max = 0.45 V SPI2_CS SPI2 chip select min = 1.35 V min = -0.3 V SPI2 master-in max = 0.63 V SPI2_MISO salve-out min = 1.17 V max = 2.1 V SPI2 master-out max = 0.45 V SPI2_MOSI slave-in...
  • Page 35 Automotive Module Series AG525R-GL QuecOpen Hardware Design WLAN_PWR_ WLAN power supply max = 0.45 V enable control 2 min = 1.35 V 1.8 V power domain. WLAN_PWR_ WLAN power supply max = 0.45 V If unused, keep enable control 1 min = 1.35 V them open.
  • Page 36 Automotive Module Series AG525R-GL QuecOpen Hardware Design Table 5: Alternate Functions of Multiplexing Pins Default Wake up Pin Name Alternate Function 1 Alternate Function 2 Reset Power Domain Remark Function Interrupt RGMII_PWR_EN BS-PD, L 1.8 V RGMII_INT RGMII BS-PD, L 1.8 V RGMII_RST BS-PD, L...
  • Page 37 Automotive Module Series AG525R-GL QuecOpen Hardware Design UART1_CTS GPIO_23 BS-PD, L 1.8 V UART1_RXD GPIO_21 BS-PU, L 1.8 V UART1_RTS GPIO_22 BS-PD, L 1.8 V DBG_TXD BS-PD, L 1.8 V DBG_RXD BS-PD, L 1.8 V PCM_SYNC I2S_WS GPIO_12 BS-PD, L 1.8 V PCM_CLK I2S_SCK...
  • Page 38 Automotive Module Series AG525R-GL QuecOpen Hardware Design USIM2_CLK BSH-PD, L 1.8/2.85 V USIM2_DATA BSH-PD, L 1.8/2.85 V USIM2_DET BS-PD, L 1.8 V SPI1_MOSI GPIO_72 BS-PD, L 1.8 V SPI1_CS GPIO_74 BS-PD, L 1.8 V SPI1_CLK GPIO_75 BS-PD, L 1.8 V SPI1_MISO GPIO_73 BS-PD, L...
  • Page 39 Automotive Module Series AG525R-GL QuecOpen Hardware Design GPIO3 BS-PD, L 1.8 V GPIO4 BS-PD, L 1.8 V GPIO GPIO5 BS-PD, L 1.8 V GPIO6 BS-PD, L 1.8 V GPIO7 BS-PD, L 1.8 V GPIO8 1.8 V GPIO9 BS-PD, L 1.8 V GPIO10 BS-PD, L 1.8 V...

  • Page 40: Operating Modes

    Automotive Module Series AG525R-GL QuecOpen Hardware Design 3.4. Operating Modes The table below briefly summarizes the various operating modes referred in the following chapters. Table 6: Overview of Operating Modes Mode Details Software is active. The module has registered on the network, and it Idle is ready to send and receive data.

  • Page 41: Usb Application With Usb Remote Wakeup Function

    Automotive Module Series AG525R-GL QuecOpen Hardware Design Figure 3: Sleep Mode Current Consumption Diagram NOTE DRX cycle index values are broadcasted by the base station through the wireless network. 3.5.1.1. USB Application with USB Remote Wakeup Function If the host supports USB suspend/resume and remote wakeup function, the following three preconditions must be met to let the module enter sleep mode.

  • Page 42: Usb Application Without Usb Remote Wakeup Function

    Automotive Module Series AG525R-GL QuecOpen Hardware Design  Sending data to the module through USB will wake up the module.  When the module has URC to report, it will send remote wake-up signals via USB bus so as to wake up the host.

  • Page 43: Airplane Mode

    Automotive Module Series AG525R-GL QuecOpen Hardware Design The following figure shows the connection between the module and the host. Figure 6: Sleep Mode Application without Suspend Function Switching on the power switch to supply power to USB_VBUS will wake up the module. NOTE Please pay attention to the level match shown in dotted line between the module and the host.

  • Page 44: Decrease Voltage Drop

    Automotive Module Series AG525R-GL QuecOpen Hardware Design Table 7: VBAT and GND Pins Pin Name Pin No. Description Min. Typ. Max. Unit Power supply for the VBAT_BB 241, 242, 244 module’s baseband part Power supply for the VBAT_RF 109, 111, 112, 114 module’s RF part 12, 18, 26, 33, 42, 86, 92, 98, 115, 117, 118, 120, 121, 124–131,133–135, 137, 138, 140, 141, 144–151,153, 155, 156, 158, 159, 160, 162, 164, 165, 167, 168,...

  • Page 45: Reference Design For Power Supply

    Automotive Module Series AG525R-GL QuecOpen Hardware Design DC_3V8 VBAT_BB VBAT_RF 100 µF 10 pF 100 nF 33 pF 100 µF 100 nF 33 pF 10 pF Module Figure 8: VBAT Reference Design 3.6.3. Reference Design for Power Supply Power design for the module is very important, as the performance of the module largely depends on the power source.

  • Page 46: Monitor The Power Supply

    Automotive Module Series AG525R-GL QuecOpen Hardware Design 3.6.4. Monitor the Power Supply API can be used to monitor the VBAT_BB voltage value. For more details, see document [2]. 3.7. Power on and off Scenarios 3.7.1. Turn on Module with PWRKEY Table 8: PWRKEY Pin Description Pin Name Pin No.
  • Page 47 Automotive Module Series AG525R-GL QuecOpen Hardware Design Figure 11: Turn on the Module Using Keystroke The power on scenario is illustrated in the following figure. Figure 12: Power-on Timing NOTES 1. Please make sure that VBAT is stable for at least 30 ms before pulling down PWRKEY pin. 2.

  • Page 48: Turn On Module With Pon_1

    Automotive Module Series AG525R-GL QuecOpen Hardware Design 3.7.2. Turn on Module with PON_1 Table 9: PON_1 Pin Description Pin Name Pin No. Description Comment Driving it high will turn on the module Valid trigger range: PON_1 automatically 0.78 V~1.89 V. When the module is powered off, drive PON_1 high for at least 500 ms will turn on the module automatically.

  • Page 49: Turn Off Module Using Api Interface

    Automotive Module Series AG525R-GL QuecOpen Hardware Design VBA T ≥ 2 s PWRKEY Module Power- down procedure RUNNING Status VDD_ EXT Figure 14: Power-off Timing 3.7.3.2. Turn off Module Using API Interface It is also a safe way to use API interface to turn off the module, which is similar to turning off the module via PWRKEY Pin.
  • Page 50 Automotive Module Series AG525R-GL QuecOpen Hardware Design Table 10: RESET Pin Description Pin Name Pin No. Description DC Characteristics Comment max = 1.89 V RESET Reset the module min = 1.17 V max = 0.63 V The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or button can be used to control the RESET.

  • Page 51: U)Sim Interfaces

    Automotive Module Series AG525R-GL QuecOpen Hardware Design Figure 17: Timing of Resetting Module NOTE Please assure that there is no large capacitance on PWRKEY and RESET pins. 3.9. (U)SIM Interfaces The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Both 1.8 V and 3.0 V (U)SIM cards are supported.
  • Page 52 Automotive Module Series AG525R-GL QuecOpen Hardware Design USIM2_DET (U)SIM2 card hot-plug detect The module supports (U)SIM card hot-plug via the USIM_DET pin and either low level or high level detection is supported. The function is disabled by default and can be enabled by AT+QSIMDET. See document [3] for more details of the command.

  • Page 53: Usb Interfaces

    Automotive Module Series AG525R-GL QuecOpen Hardware Design To enhance the reliability and availability of the (U)SIM card, follow the criteria below in the (U)SIM circuit design:  Keep the placement of (U)SIM card connector as close to the module as possible. Keep the trace length as less than 200 mm as possible.
  • Page 54 Automotive Module Series AG525R-GL QuecOpen Hardware Design standard specification. USB_DM AI/AO USB differential data bus (-) Require differential impedance of 90 Ω. USB_SS_TX_P USB 3.0 super-speed transmit (+) Compliant with USB 3.0 USB_SS_TX_M USB 3.0 super-speed transmit (-) standard specification. Require differential USB_SS_RX_P USB 3.0 super-speed receive (+)

  • Page 55: Uart Interfaces

    Automotive Module Series AG525R-GL QuecOpen Hardware Design To ensure signal integrity of USB data lines, components R1, R2 and L1 must be placed close to the module, and also these resistors should be placed close to each other. The capacitors C1 and C2 should be placed near the module.
  • Page 56 Automotive Module Series AG525R-GL QuecOpen Hardware Design Table 13: Pin Definition of UART1 Interface Pin Name Pin No. Description Comment UART1_CTS UART1 clear to send UART1_RTS UART1 request to send 1.8 V power domain. Can be configured to GPIOs. UART1_TXD UART1 transmit UART1_RXD UART1 receive...
  • Page 57 Automotive Module Series AG525R-GL QuecOpen Hardware Design The module provides 1.8 V UART interfaces. A level translator should be used if customers’ application is equipped with a 3.3 V UART interface. A level translator TXS0104E-Q1 provided by Texas Instruments (visit http://www.ti.com for more information) is recommended. The following figure shows a reference design.

  • Page 58: I2S And I2C Interfaces

    Automotive Module Series AG525R-GL QuecOpen Hardware Design 3.12. I2S and I2C Interfaces The module provides I2S and I2C interfaces for audio function design. Table 17: Pin Definition of I2S Interface Pin Name Pin No. Description Comment CDC_RST Codec reset I2S_MCLK Clock output for codec 1.8 V power domain.
  • Page 59 Automotive Module Series AG525R-GL QuecOpen Hardware Design NOTE The module works as a master device pertaining to I2C interface. 3.13. SDIO Interface The module provides an SDIO interface. It is recommended to use the interface for eMMC application. Table 19: Pin Definition of SDIO Interface Pin Name Pin No.
  • Page 60 Automotive Module Series AG525R-GL QuecOpen Hardware Design The following is a reference design of SDIO interface for eMMC application. VDD_1V8 VDD_1.8V R1 0R SDC1_DATA_0 DAT0 VCCQ R2 0R SDC1_DATA_1 DAT1 1 µF 100 nF R3 0R SDC1_DATA_2 DAT2 VDD_3V R4 0R SDC1_DATA_3 DAT3 R5 0R...
  • Page 61 Automotive Module Series AG525R-GL QuecOpen Hardware Design 3.14. SPI Interfaces The module provides two SPI interfaces supporting only master mode. The maximum clock frequency of SPI is up to 50 MHz. Table 20: Pin Definition of SPI Interfaces Pin Name Pin No.
  • Page 62 Automotive Module Series AG525R-GL QuecOpen Hardware Design Table 21: Parameters of SPI Interface Timing Parameter Description Min. Typ. Max. Unit SPI clock period 20.0 t(ch) SPI clock high-level time t(cl) SPI clock low-level time t(mov) SPI master data output valid time -5.0 t(mis) SPI master data input setup time...
  • Page 63 Automotive Module Series AG525R-GL QuecOpen Hardware Design RGMII_CTL_RX RGMII receive control RGMII_RX_2 RGMII receive data bit 2 RGMII_RX_3 RGMII receive data bit 3 RGMII_CK_RX RGMII receive clock RGMII_TX_0 RGMII transmit data bit 0 RGMII_CTL_TX RGMII transmit control RGMII_TX_1 RGMII transmit data bit 1 RGMII_TX_2 RGMII transmit data bit 2 RGMII_CK_TX...
  • Page 64 Automotive Module Series AG525R-GL QuecOpen Hardware Design The following figure shows a reference design of RGMII interface with PHY application. Figure 28: Reference Circuit of RGMII Interface with PHY Application In order to enhance the reliability and availability of customers’ application, please follow the criteria below in the Ethernet PHY circuit design: ...
  • Page 65 Automotive Module Series AG525R-GL QuecOpen Hardware Design  Spacing to all other signals is larger than three times of line width.  Resistors R7–R12 should be placed near the module. Resistor R1–R6 should be placed near the Ethernet PHY. The value of R1–R16 varies with the selection of PHY. 3.16.
  • Page 66 Automotive Module Series AG525R-GL QuecOpen Hardware Design 1.8 V power domain. BT_UART_RTS BT UART request to send Can be configured to GPIOs. BT_UART_CTS BT UART clear to send PCM_SYNC PCM data frame sync PCM_CLK PCM data bit clock PCM_IN PCM data input PCM_OUT PCM data output Others interfaces...
  • Page 67 Automotive Module Series AG525R-GL QuecOpen Hardware Design VDD_EXT 100K 100K PCIE_CLKREQ PCIE_CLKREQ_N PCIE_WAKE PCIE_WAKE PCIE_RST PCIE_RST PCIE_REFCLK_P PCIE_REFCLKP PCIE_REFCLKM PCIE_REFCLK_M 100 nF PCIE_TX_M PCIE_RXM 100 nF PCIE_TX_P PCIE_RXP 100 nF PCIE_RX_M PCIE_TXM 100 nF PCIE_RX_P PCIE_TXP COEX_UART_ RXD COEX_UART_ TXD COEX_UART_ TXD COEX_UART_ RXD BT_UART_TXD...
  • Page 68 Automotive Module Series AG525R-GL QuecOpen Hardware Design The following principles of PCIe interface design should be complied with, so as to meet PCIe Gen2 specifications.  It is important to route the PCIe signal traces as differential pairs with ground surrounded. And the differential impedance is 95 Ω...
  • Page 69 Automotive Module Series AG525R-GL QuecOpen Hardware Design ADC0 Voltage Range 1.875 ADC1 Voltage Range 1.875 ADC2 Voltage Range 1.875 ADC Resolution bits ADC Sample Rate NOTES The input voltage for each ADC interface must not exceed its corresponding voltage range. It is prohibited to supply any voltage to ADC pins when VBAT is removed.

  • Page 70: Gpio Interfaces

    Automotive Module Series AG525R-GL QuecOpen Hardware Design 3.19. GPIO Interfaces The module provides 11 GPIOs. Table 27: Pin Definition of GPIOs Pin Name Pin No. Description Comment GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 1.8 V power domain. GPIO6 General-purpose input/output If unused, keep them open.

  • Page 71: Antenna Interfaces

    Automotive Module Series AG525R-GL QuecOpen Hardware Design Antenna Interfaces The module includes one main antenna interface (ANT_MAIN) and one Rx-diversity antenna interface (ANT_DIV) which is used to resist the fall of signals caused by high speed movement and multipath effect. The antenna ports have an impedance of 50 Ω.
  • Page 72 Automotive Module Series AG525R-GL QuecOpen Hardware Design WCDMA B3 1710–1785 1805–1880 WCDMA B4 1710–1755 2110–2155 WCDMA B5 824–849 869–894 WCDMA B8 880–915 925–960 WCDMA B9 1749.9–1784.9 1844.9–1879.9 WCDMA B19 830–845 875–890 LTE-FDD B1 1920–1980 2110–2170 LTE-FDD B2 1850–1910 1930–1990 LTE-FDD B5 824–849 869–894 LTE-FDD B7...

  • Page 73: Reference Design Of Rf Antenna Interfaces

    Automotive Module Series AG525R-GL QuecOpen Hardware Design LTE-FDD B32 1452–1496 LTE-TDD B34 2010–2025 2010–2025 LTE-TDD B38 2570–2620 2570–2620 LTE-TDD B39 1880–1920 1880–1920 LTE-TDD B40 2300–2400 2300–2400 LTE-TDD B41 2555–2655 2555–2655 LTE-TDD B66 1710–1780 2110–2200 LTE-TDD B71 663–698 617–652 NOTE LTE-FDD B29, B30 and B32 support Rx only. 4.1.3.

  • Page 74: Reference Design Of Rf Layout

    Automotive Module Series AG525R-GL QuecOpen Hardware Design NOTES ANT_DIV function is enabled by default. command can be used to disable AT+QCFG="diversity",0 receive diversity. See document [3] for details of the command. 4.1.4. Reference Design of RF Layout For user’s PCB, the characteristic impedance of all RF traces should be controlled to 50 Ω. The impedance of the RF traces is usually determined by the trace width (W), the materials’...
  • Page 75 Automotive Module Series AG525R-GL QuecOpen Hardware Design Figure 34: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 35: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) To ensure RF performance and reliability, the following principles should be complied with in RF layout design: ...

  • Page 76: Antenna Installation

    Automotive Module Series AG525R-GL QuecOpen Hardware Design 4.2. Antenna Installation 4.2.1. Antenna Requirements The following table shows the requirements on the main antenna and the Rx-diversity antenna. Table 30: Antenna Requirements Type Requirements VSWR: ≤ 2 Efficiency: > 30% Max input power: 50 W Input impedance: 50 Ω...

  • Page 77: Recommended Rf Connector For Antenna Installation

    Automotive Module Series AG525R-GL QuecOpen Hardware Design 4.2.2. Recommended RF Connector for Antenna Installation If RF connector is used for antenna connection, it is recommended to use the HFM connector provided by Rosenberger. Figure 36: Description of the HFM Connector For more details, visit https://www.rosenbergerap.com.

  • Page 78: Reliability, Radio And Electrical Characteristics

    Automotive Module Series AG525R-GL QuecOpen Hardware Design Reliability, Radio and Electrical Characteristics 5.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 31: Absolute Maximum Ratings Parameter Min.

  • Page 79: Power Supply Ratings

    Automotive Module Series AG525R-GL QuecOpen Hardware Design 5.2. Power Supply Ratings Table 32: Power Supply Ratings Parameter Description Conditions Min. Typ. Max. Unit The actual input voltages must be kept VBAT_BB and VBAT between the minimum and maximum VBAT_RF values. USB connection USB_VBUS 5.25...

  • Page 80: Current Consumption

    Automotive Module Series AG525R-GL QuecOpen Hardware Design 5.4. Current Consumption Table 34: Module Current Consumption (25 °C, 3.8 V Power Supply) Description Conditions Typ. Unit OFF state Power down 0.021 AT+CFUN=0 (USB disconnected) 1.144 GSM850 DRX = 2 (USB disconnected) 3.183 GSM850 DRX = 5 (USB disconnected) 2.128...
  • Page 81 Automotive Module Series AG525R-GL QuecOpen Hardware Design WCDMA PF = 256 (USB disconnected) 2.019 WCDMA PF = 512 (USB disconnected) 1.925 LTE-FDD PF = 32 (USB disconnected) 4.123 LTE-FDD PF = 64 (USB disconnected) 2.968 LTE-FDD PF = 64 (USB suspend) LTE-FDD PF = 128 (USB disconnected) 3.208 LTE-FDD PF = 256 (USB disconnected)
  • Page 82 Automotive Module Series AG525R-GL QuecOpen Hardware Design EGSM900 3DL/2UL @ 32 dBm 518.5 EGSM900 2DL/3UL @ 30dBm 618.1 EGSM900 1DL/4UL @ 29 dBm 690.5 DCS1800 4DL/1UL @ 29.5 dBm 236.8 DCS1800 3DL/2UL @ 29.0dBm 367.6 DCS1800 2DL/3UL @ 26.5 dBm 426.2 DCS1800 1DL/4UL @ 25.5 dBm 501.9...
  • Page 83 Automotive Module Series AG525R-GL QuecOpen Hardware Design PCS1900 2DL/3UL @ 23.0dBm 322.2 PCS1900 1DL/4UL @ 22.0dBm 371.2 WCDMA B1 HSDPA @ 23.0 dBm 590.7 WCDMA B2 HSDPA @ 23.0 dBm 656.7 WCDMA B3 HSDPA @ 23.0 dBm 610.42 WCDMA B4 HSDPA @ 23.0 dBm 650.27 WCDMA B5 HSDPA @ 23.0 dBm 588.94...
  • Page 84 Automotive Module Series AG525R-GL QuecOpen Hardware Design LTE-FDD B9 @ 23.0dBm 597.53 LTE-FDD B11 @ 23.0dBm 674.67 LTE-FDD B12 @ 23.0dBm 595.3 LTE-FDD B13 @ 23.0dBm 661.65 LTE-FDD B17 @ 23.0dBm 596.13 LTE-FDD B18 @ 23.0dBm 636.57 LTE-FDD B19 @ 23.0dBm 627.77 LTE-FDD B20 @ 23.0dBm 617.46...

  • Page 85: Rf Output Power

    Automotive Module Series AG525R-GL QuecOpen Hardware Design EGSM900, PCL = 19 @ 5.0dBm 125.1 DCS1800, PCL = 0 @ 30 dBm 248.9 DCS1800, PCL = 7 @ 16.0dBm 139.2 DCS1800, PCL = 15 @ 0dBm PCS1900, PCL = 0 @ 30 dBm 255.6 PCS1900, PCL = 7 @ 16.0dBm 138.8...
  • Page 86 Automotive Module Series AG525R-GL QuecOpen Hardware Design WCDMA B1 24dBm +1/-3 dB < -49 dBm WCDMA B2 24dBm +1/-3 dB < -49 dBm WCDMA B3 24dBm +1/-3 dB < -49 dBm WCDMA B4 24dBm +1/-3 dB < -49 dBm WCDMA B5 24dBm +1/-3 dB <...

  • Page 87: Rf Receiving Sensitivity

    Automotive Module Series AG525R-GL QuecOpen Hardware Design LTE-FDD B26 23 dBm ±2 dB < -39 dBm LTE-FDD B28 23 dBm ±2 dB < -39 dBm LTE-FDD B29 23 dBm ±2 dB < -39 dBm LTE-FDD B30 23 dBm ±2 dB <...
  • Page 88 Automotive Module Series AG525R-GL QuecOpen Hardware Design WCDMA B1 -112 -112 -114 -106.7 WCDMA B2 -112 -112.5 -113 -106.7 WCDMA B3 -113 -113 -114.5 -106.7 WCDMA B4 -112.5 -113 -114 -106.7 WCDMA B5 -110 -113 -114.5 -106.7 WCDMA B8 -112 -113.5 -114.5 -106.7...

  • Page 89: Electrostatic Discharge

    Automotive Module Series AG525R-GL QuecOpen Hardware Design LTE-FDD B26(10 MHz) -100 -100.12 -103.02 -94.3 LTE-FDD B28 (10 MHz) -100.1 -100.02 -103.32 -94.8 LTE-FDD B29 (10 MHz) -99.22 -100.22 -102.72 -93.3 LTE-FDD B30 (10 MHz) -97.82 -98.82 -101.32 -95.3 LTE-FDD B32 (10 MHz) -94.82 -96.82 -98.82...

  • Page 90: Thermal Consideration

    Automotive Module Series AG525R-GL QuecOpen Hardware Design 5.8. Thermal Consideration In order to achieve better performance of the module, it is recommended to comply with the following principles for thermal consideration:  On customers’ PCB design, please keep placement of the module away from heating sources, especially high power components such as ARM processor, audio power amplifier, power supply, etc.
  • Page 91 Automotive Module Series AG525R-GL QuecOpen Hardware Design Figure 38: Referenced Heatsink Design (Heatsink at the Backside of Customers’ PCB) NOTES For better performance, the maximum temperature of the internal BB chip should be kept below 105 °C. When the maximum temperature of the BB chip reaches or exceeds 105 °C, the module works normal but provides reduced performance (such as RF output power and data rate).

  • Page 92: Mechanical Dimensions

    Automotive Module Series AG525R-GL QuecOpen Hardware Design Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are ±0.05 mm unless otherwise specified. 6.1. Mechanical Dimensions Figure 39: Module Top and Side Dimensions AG525R-GL_QuecOpen_Hardware_Design 91 / 104...
  • Page 93 Automotive Module Series AG525R-GL QuecOpen Hardware Design Figure 40: Module Bottom Dimensions (Top View) NOTE The package warpage level of the module conforms to JEITA ED-7306 standard. AG525R-GL_QuecOpen_Hardware_Design 92 / 104...

  • Page 94: Recommended Footprint

    Automotive Module Series AG525R-GL QuecOpen Hardware Design 6.2. Recommended Footprint Figure 41: Recommended Footprint (Top View) NOTE For convenient maintenance of the module, please keep about 3 mm between the module and other components on the motherboard. AG525R-GL_QuecOpen_Hardware_Design 93 / 104...

  • Page 95: Top And Bottom Views

    AG525R-GL QuecOpen Hardware Design 6.3. Top and Bottom Views Figure 42: Top View of the Module Figure 43: Bottom View of the Module NOTE These are renderings of the module. For authentic appearance, see the module received from Quectel. AG525R-GL_QuecOpen_Hardware_Design 94 / 104...

  • Page 96: Storage, Manufacturing And Packaging

    Automotive Module Series AG525R-GL QuecOpen Hardware Design Storage, Manufacturing and Packaging 7.1. Storage The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: The temperature should be 23 ±5 °C and the relative humidity should be 35–60 %.

  • Page 97: Manufacturing And Soldering

    Automotive Module Series AG525R-GL QuecOpen Hardware Design NOTE This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. 2. To avoid blistering, layer separation and other soldering issues, it is forbidden to expose the modules to the air for a long time. It is recommended to start the solder reflow process within 24 hours after the package is removed if the temperature and moisture do not conform to IPC/JEDEC J-STD-033.

  • Page 98: Packaging

    Automotive Module Series AG525R-GL QuecOpen Hardware Design Table 38: Recommended Thermal Profile Parameters Factor Recommendation Soak Zone Max slope 1–3 °C/s Soak time (between A and B: 150°C and 200°C) 70–120 s Reflow Zone Max slope 2–3 °C/s Reflow time (D: over 220°C) 45–70 s Max temperature 238–246 °C...
  • Page 99 Automotive Module Series AG525R-GL QuecOpen Hardware Design Figure 45: Tape Specifications Figure 46: Reel Specifications AG525R-GL_QuecOpen_Hardware_Design 98 / 104...

  • Page 100: Appendix A References

    EVB User Guide for Automotive Modules Quectel_AG525R-GL_QuecOpen_Developer_Guide AG525R-GL QuecOpen Developer Guide Quectel_AG525R-GL_AT_Commands_Manual AG525R-GL AT Commands Manual Quectel_RF_Layout_Application_Note RF Layout Application Note Thermal Design Guide for Quectel LTE Quectel_LTE_Module_Thermal_Design_Guide (LTE Standard/LTE-A/Automotive) modules Quectel Module Secondary SMT Quectel_Module_Secondary_SMT_Application_Note Application Note AG525R-GL QuecOpen Reference...
  • Page 101 Automotive Module Series AG525R-GL QuecOpen Hardware Design Clear To Send DC-HSPA+ Dual-carrier High Speed Packet Access DFOTA Delta Firmware Upgrade Over The Air Downlink Data Terminal Ready Discontinuous Transmission Enhanced Full Rate Electrostatic Discharge EVDO Evolution-Data Optimized Frequency Division Duplex Full Rate GLObalnaya NAvigatsionnaya Sputnikovaya Sistema, the Russian Global GLONASS...
  • Page 102 Automotive Module Series AG525R-GL QuecOpen Hardware Design Mobile Originated Mobile Station (GSM engine) Mobile Terminated Password Authentication Protocol Printed Circuit Board Protocol Data Unit Point-to-Point Protocol Peak Pulse Power Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying Radio Frequency RHCP Right Hand Circularly Polarized Receive SIMO...
  • Page 103 Automotive Module Series AG525R-GL QuecOpen Hardware Design Vmin Minimum Voltage Value Maximum Input High Level Voltage Value Minimum Input High Level Voltage Value Maximum Input Low Level Voltage Value Minimum Input Low Level Voltage Value Absolute Maximum Input Voltage Value Absolute Minimum Input Voltage Value Maximum Output High Level Voltage Value Minimum Output High Level Voltage Value...

  • Page 104: Appendix B Gprs Coding Schemes

    Automotive Module Series AG525R-GL QuecOpen Hardware Design Appendix B GPRS Coding Schemes Table 41: Description of Different Coding Schemes CS-1 CS-2 CS-3 CS-4 Scheme Code Rate Pre-coded USF Radio Block excl.USF and BCS Tail Coded Bits Punctured Bits 9.05 13.4 15.6 21.4 Data Rate Kb/s...

  • Page 105: Appendix C Gprs Multi-Slot Classes

    Automotive Module Series AG525R-GL QuecOpen Hardware Design Appendix C GPRS Multi-slot Classes Twenty-nine classes of GPRS multi-slot modes are defined for MS in GPRS specification. Multi-slot classes are product dependent, and determine the maximum achievable data rates in both the uplink and downlink directions.
  • Page 106 Automotive Module Series AG525R-GL QuecOpen Hardware Design AG525R-GL_QuecOpen_Hardware_Design 105 / 104...

  • Page 107: Appendix D Edge Modulation And Coding Schemes

    Automotive Module Series AG525R-GL QuecOpen Hardware Design Appendix D EDGE Modulation and Coding Schemes Table 43: EDGE Modulation and Coding Schemes Coding Scheme Modulation Coding Family 1 Timeslot 2 Timeslot 4 Timeslot CS-1: GMSK 9.05 kbps 18.1 kbps 36.2 kbps CS-2: GMSK 13.4 kbps...

Table of Contents