Lcm Interfaces - Quectel SG368Z Series Hardware Design

b) Control the differential impedance to 100 Ω ± 10 %;
c) Control intra-lane length matching within 0.3 mm.
d) Control the length matching between clock signal traces and data signals traces within 12 mm.

4.10.3. LCM Interfaces

Table 26: Pins Description of LCM Interfaces
Pin Name
LCD1_RST
DSI0_CLK_N
DSI0_CLK_P
DSI0_LN0_N
DSI0_LN0_P
DSI0_LN1_N
DSI0_LN1_P
DSI0_LN2_N
DSI0_LN2_P
DSI0_LN3_N
DSI0_LN3_P
DSI1_CLK_N
DSI1_CLK_P
DSI1_LN0_N
DSI1_LN0_P
DSI1_LN1_N
DSI1_LN1_P
DSI1_LN2_N
DSI1_LN2_P
SG368Z_Series_Hardware_Design
Pin No. I/O
322 DO
37 AO
36 AO
47 AO
46 AO
42 AO
41 AO
32 AO
31 AO
27 AO
26 AO
33 AO
29 AO
43 AO
39 AO
38 AO
34 AO
28 AO
24 AO
Description
LCD1 reset
LCD0 MIPI clock (-)
LCD0 MIPI clock (+)
LCD0 MIPI lane 0 data (-)
LCD0 MIPI lane 0 data (+)
LCD0 MIPI lane 1 data (-)
LCD0 MIPI lane 1 data (+)
LCD0 MIPI lane 2 data (-)
LCD0 MIPI lane 2 data (+)
LCD0 MIPI lane 3 data (-)
LCD0 MIPI lane 3 data (+)
LCD1 MIPI clock (-)
LCD1 MIPI clock (+)
LCD1 MIPI lane 0 data (-)
LCD1 MIPI lane 0 data (+)
LCD1 MIPI lane 1 data (-)
LCD1 MIPI lane 1 data (+)
LCD1 MIPI lane 2 data (-)
LCD1 MIPI lane 2 data (+)
Smart Module Series
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