Quectel SG368Z Series Hardware Design page 22

USB1_DM
USB1_SS_TX_P
USB1_SS_TX_M
USB1_SS_RX_P
USB1_SS_RX_M
USB2_DP
USB2_DM
USB3_DP
USB3_DM
PCIe Interfaces
Pin Name
PCIE1_TX_P
PCIE1_TX_M
PCIE1_RX_P
PCIE1_RX_M
PCIE1_REFCLK_P
PCIE1_REFCLK_M
PCIE1_CLKREQ_N
PCIE1_WAKE_N
PCIE1_RST_N
PCIE2_TX0_P
PCIE2_TX0_M
PCIE2_TX1_P
PCIE2_TX1_M
SG368Z_Series_Hardware_Design
USB1 2.0 differential
83 AIO
data (-)
USB1 3.0 transmit
84 AO
(+)
USB1 3.0 transmit
88 AO
(-)
89 AI USB1 3.0 receive (+)
92 AI USB1 3.0 receive (-)
USB2 2.0 differential
289 AIO
data (+)
USB2 2.0 differential
292 AIO
data (-)
USB3 2.0 differential
295 AIO
data (+)
USB3 2.0 differential
297 AIO
data (-)
Pin No. I/O Description
90 AO PCIe1 transmit (+)
91 AO PCIe1 transmit (-)
86 AI PCIe1 receive (+)
87 AI PCIe1 receive (-)
PCIe1 reference
81 AO
clock (+)
PCIe1 reference
82 AO
clock (-)
366 DI PCIe1 clock request
367 DI PCIe1 wake up
333 DO PCIe1 reset
58 AO PCIe2 transmit 0 (+)
54 AO PCIe2 transmit 0 (-)
63 AO PCIe2 transmit 1 (+)
59 AO PCIe2 transmit 1 (-)
Smart Module Series
DC
Comment
Characteristics
VCCIO5
VCCIO5
VCCIO5
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