Quectel SG368Z Series Hardware Design page 23

PCIE2_RX0_P
PCIE2_RX0_M
PCIE2_RX1_P
PCIE2_RX1_M
PCIE2_REFCLK_P
PCIE2_REFCLK_M
PCIE2_CLKREQ0_
N
PCIE2_WAKE0_N
PCIE2_RST0_N
PCIE2_CLKREQ1_
N
PCIE2_WAKE1_N
PCIE2_RST1_N
SD Card Interface
Pin Name
SD_VDD
SD_CLK
SD_CMD
SD_DATA0
SG368Z_Series_Hardware_Design
68 AI PCIe2 receive 0 (+)
64 AI PCIe2 receive 0 (-)
73 AI PCIe2 receive 1 (+)
69 AI PCIe2 receive 1 (-)
PCIe2 reference
53 AI
clock (+)
PCIe2 reference
49 AI
clock (-)
PCIe2 channel 0
364 DIO
clock request
PCIe2 channel 0
363 DIO
wake up
PCIe2 channel 0
362 DIO
reset
PCIe2 channel 1
368 DI
clock request
PCIe2 channel 1
369 DI
wake up
PCIe2 channel 1
358 DO
reset
Pin No. I/O Description
SD card power
262 PO
supply
252 DO SD card clock
247 DIO SD card command
246 DIO SDIO data bit 0
Smart Module Series
If unused, connect
this pin to ground.
If unused, connect
this pin to ground.
When PCIe2 is
configured in PCIe
× 2 lane mode,
VCCIO5
this pin is used for
clock request
function.
When PCIe2 is
configured in PCIe
VCCIO5 × 2 lane mode,
this pin is used for
wake up function.
When PCIe2 is
configured in PCIe
VCCIO5 × 2 lane mode,
this pin is used for
reset function.
VCCIO5
VCCIO5
VCCIO5
DC
Comment
Characteristics
Dedicated for SD
Vnom = VBAT card power
supply.
VCCIO3
VCCIO3
VCCIO3
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