Quectel SG368Z Series Hardware Design page 28

Smart module
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RGMII0_TX_CLK
RGMII0_MDC
RGMII0_MDIO
RGMII0_
REFCLKOUT
RGMII0_MCLK
RGMII1_RX0
RGMII1_RX1
RGMII1_RX2
RGMII1_RX3
RGMII1_RX_CTL
RGMII1_RX_CLK
RGMII1_TX0
RGMII1_TX1
RGMII1_TX2
RGMII1_TX3
RGMII1_TX_CTL
RGMII1_TX_CLK
RGMII1_MDC
SG368Z_Series_Hardware_Design
RGMII0 transmit
163
DO
clock
RGMII0
181
DO
management data
clock
RGMII0
185
OD
management data
input/output
RGMII0 reference
160
DO
clock output
177
DI
RGMII0 clock input
RGMII1 receive data
296
DI
bit 0
RGMII1 receive data
294
DI
bit 1
RGMII1 receive data
308
DI
bit 2
RGMII1 receive data
307
DI
bit 3
RGMII1 receive
293
DI
control
RGMII1 receive
304
DI
clock
RGMII1 transmit
305
DO
data bit 0
RGMII1 transmit
303
DO
data bit 1
RGMII1 transmit
312
DO
data bit 2
RGMII1 transmit
310
DO
data bit 3
RGMII1 transmit
298
DO
control
RGMII1 transmit
306
DO
clock
RGMII1
290
DO
management data
Smart Module Series
Only SG368Z-AP
VCCIO4
supports this pin.
Only SG368Z-AP
VCCIO4
supports this pin.
Only SG368Z-AP
VCCIO4
supports this pin.
The output
frequency of
VCCIO4
reference clock is
25 MHz.
The output
frequency of
reference clock is
VCCIO4
125 MHz;
Only SG368Z-AP
supports this pin.
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
27 / 113

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