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VCCIOx
RGMIIx_TX0
RGMIIx_TX1
RGMIIx_TX2
RGMIIx_TX3
RGMIIx_TX_CTL
RGMIIx_TX_CLK
RGMIIx_RX0
RGMIIx_RX1
RGMIIx_RX2
RGMIIx_RX3
RGMIIx_RX_CTL
RGMIIx_RX_CLK
RGMIIx_MDC
RGMIIx_MDIO
RGMIIx_MCLK
(Option)
RGMII0_REFCLKOUT
Module
Figure 29: Reference Design of RGMII Interface PHY with Module's 25 MHz Clock
NOTE
1.
SG368Z-AP supports RGMII0 and RGMII1 interfaces, while SG368Z-WF only supports RGMII1
interface. RGMII0 uses GMAC0 controller and RGMII1 uses GMAC1 controller.
2.
The power domain of RGMII interface is 1.8 V. Please pay attention to level matching with the voltage
of the PHY.
3.
RGMII_MCLK is an optional function and can be left unconnected.
4.
For the design of PHY end, please refer to the reference design of the PHY chip. The designs above
are for reference only.
5.
If you choose the multiplexed SGMII interface, the used MDC/MDIO needs to match the GMACx
used, that is, if SGMII uses GMAC0, select RGMII0_MDC/RGMII0_MDIO, and if SGMII uses
GMAC1, select RGMII1_MDC/RGMII1_MDIO.
6.
If you choose the multiplexed QSGMII interface, you can choose RGMII0_MDC/RGMII0_MDIO or
RGMII1_MDC/RGMII1_MDIO for MDC/MDIO functions.
SG368Z_Series_Hardware_Design
22R
R1
22R
R2
22R
R3
R4
22R
R5
22R
22R
R6
22R
R14
R17
22R
GPIO
GPIO
R13
1.5K
R7
22R
22R
R8
22R
R9
R10
22R
22R
R11
22R
R12
R15
R16
Smart Module Series
VCCIO_PHY
PHY_TX0
PHY_TX1
PHY_TX2
PHY_TX3
PHY_TX_CTL
PHY_TX_CLK
PHY_RX0
PHY_RX1
PHY_RX2
PHY_RX3
PHY_RX_CTL
PHY_RX_CLK
PHY_MDC
PHY_MDIO
CLK_OUT
XTAL_IN
XTAL_OUT/EX_CLK
INT
PHYRST
PHY
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