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PWM
GPIO
EDP_DET
EDP_AUX_N
EDP_AUX_P
EDP_ML0_P
EDP_ML0_N
EDP_ML1_P
EDP_ML1_N
EDP_ML2_P
EDP_ML2_N
EDP_ML3_P
EDP_ML3_N
GND
Module
NOTE
1.
Confirm that whether level-shift is needed for PWM, BL_EN, HPD and other signals according to the
selected module pins and eDP LCD specifications.
2.
For LCDs that support eDP V1.2a and above protocols, R1 and R2 are not mounted.
3.
If the eDP LCD has requirements on the power-up timing, the module's GPIO can be selected for
timing control.
4.
If the application scenario involves frequent plugging and unplugging of the eDP connector or has
high requirements for ESD protection, it is recommended to reserve a TVS near the connector, and
the TVS junction capacitance should not exceed 0.4 pF.
5.
EDP_DET is optional and can be configured as required.
SG368Z_Series_Hardware_Design
VCC_3V3
Level shift
Level shift
Level shift
C5
100 nF
C6
100 nF
C7
100 nF
C8
100 nF
C9
100 nF
C10
100 nF
C11
100 nF
C12
100 nF
C13
100 nF
C14
100 nF
VCC_12V
Figure 17: Reference Design of eDP Interface
C1
C2
100 nF
4.7 μF
R1
100K
R2
C3
C4
100K
100 nF
4.7 μF
Smart Module Series
1
VDDIN
2
VDDIN
3
VDDIN
4
NC
5
GND
6
NC
7
NC
8
PWM
9
NC
10
BL_EN
11
HPD
12
GND
13
DAUXN
14
DAUXP
15
GND
16
DRX0P
17
DRX0N
18
GND
19
DRX1P
20
DRX1N
21
GND
22
DRX2P
23
DRX2N
24
GND
25
DRX3P
26
DRX3N
27
GND
28
VLED
29
NC
30
NC
eDP LCD
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