Quectel SG368Z Series Hardware Design page 77

Smart module
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RGMII1_RX3
RGMII1_RX_CTL
RGMII1_RX_CLK
RGMII1_TX0
RGMII1_TX1
RGMII1_TX2
RGMII1_TX3
RGMII1_TX_CTL
RGMII1_TX_CLK
RGMII1_MDC
RGMII1_MDIO
RGMII1_
REFCLKOUT
RGMII1_MCLK
SG368Z_Series_Hardware_Design
307
DI
RGMII1 receive data bit 3
293
DI
RGMII1 receive control
304
DI
RGMII1 receive clock
305
DO
RGMII1 transmit data bit 0
303
DO
RGMII1 transmit data bit 1
312
DO
RGMII1 transmit data bit 2
310
DO
RGMII1 transmit data bit 3
298
DO
RGMII1 transmit control
306
DO
RGMII1 transmit clock
RGMII1 management data
290
DO
clock
RGMII1 management data
286
OD
input/output
RGMII1 reference clock
288
DO
output
278
DI
RGMII1 clock input
Smart Module Series
The output frequency of
reference clock is 25 MHz.
The output frequency of
reference clock is 125 MHz.
76 / 113

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