Hdmi Interface - Quectel SG368Z Series Hardware Design

Table 23: eDP Interface Trace Length Inside the Module (Unit: mm)
Pin Name Pin No.
EDP_ML0_P 136
EDP_ML0_N 132
EDP_ML1_P 131
EDP_ML1_N 127
EDP_ML2_P 126
EDP_ML2_N 122
EDP_ML3_P 121
EDP_ML3_N 117
EDP_AUX_P 141
EDP_AUX_N 137
To ensure performance, the following principles should be complied with when designing eDP interface:
⚫ Special attention should be paid to the pin description of eDP interface. Different eDP device will
have varied definitions for their corresponding connectors. Ensure that the devices and the
connectors are correctly connected.
eDP are high-speed signal traces, supporting maximum data rate up to 2.7 Gbps. The differential
⚫
impedance should be controlled to 100 Ω. Additionally, it is recommended to route the traces on the
inner layer of PCB and do not cross it with other traces. To avoid crosstalk, a clearance of 4 times the
trace width is recommended among eDP signal traces. During impedance matching, do not connect
eDP signal traces to GND on different planes to ensure impedance consistency.
⚫ It is recommended to select a TVS of low capacitance for ESD protection and the recommended
parasitic capacitance should be lower than 0.4 pF.
⚫ Route eDP traces according to the following requirements:
a) The total trace length should not exceed 150 mm;
b) Control the differential impedance to 100 Ω ± 10 %;
c) Control intra-lane length matching within 0.3 mm.

4.10.2. HDMI Interface

The module supports HDMI 2.0 and supports 1 group of 3-lane HDMI interface, with the maximum output
resolution up to 4096 × 2160 @ 60 fps.
SG368Z_Series_Hardware_Design
Length
33.18
33.34
31.89
31.92
34.51
34.66
31.55
31.78
30.86
30.94
Smart Module Series
Length Matching (N-P)
-0.16
-0.03
-0.15
-0.23
-0.08
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