Quectel SG368Z Series Hardware Design page 72

PCIE2_TX1_M
PCIE2_RX0_P
PCIE2_RX0_M
PCIE2_RX1_P
PCIE2_RX1_M
PCIE2_REFCLK_P
PCIE2_REFCLK_M
PCIE2_CLKREQ0_N
PCIE2_WAKE0_N
PCIE2_RST0_N
PCIE2_CLKREQ1_N
PCIE2_WAKE1_N
PCIE2_RST1_N
1 × Lane RC
Module
SG368Z_Series_Hardware_Design
59 AO PCIe2 transmit 1 (-)
68 AI PCIe2 receive 0 (+)
64 AI PCIe2 receive 0 (-)
73 AI PCIe2 receive 1 (+)
69 AI PCIe2 receive 1 (-)
53 AI PCIe2 reference clock (+)
49 AI PCIe2 reference clock (-)
364 DIO PCIe2 channel 0 clock request
363 DIO PCIe2 channel 0 wake up
362 DIO PCIe2 channel 0 reset
368 DI PCIe2 channel 1 clock request
369 DI PCIe2 channel 1 wake up
358 DO PCIe2 channel 1 reset
PCIe 2.0 REFCLK
Smart Module Series
If unused, connect this pin
to ground.
If unused, connect this pin
to ground.
When PCIe2 is configured
in PCIe × 2 lane mode, this
pin is used for clock request
function.
When PCIe2 is configured
in PCIe × 2 lane mode, this
pin is used for wake up
function.
When PCIe2 is configured
in PCIe × 2 lane mode, this
pin is used for reset
function.
1 × Lane EP
EP
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